TEXAS INSTRUMENTS Data acquisition IC - DA converter (DAC) SSOP 28 : Datasheet : Page 28

Register Map

Register Definitions

PCM1795

SLES248 – MAY 2009 ........................................................................................................................................................................................................

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Table 8. User-Programmable Function Controls (continued)

DF

FUNCTION DEFAULT REGISTER BIT PCM DSD BYPASS

FUNCTION AVAILABLE ONLY FOR READ

Zero detection flag Not zero = 0 ZFGL (for left channel)

Register 22 Yes Yes Yes

Not zero, zero detected Zero detected = 1 ZFGR (for right channel)

Device ID (at TDMCA) — Register 23 ID[4:0] Yes No No

The mode control register map is shown in Table 9 . Registers 16 to 21 include an R/ W bit that determines

whether a register read (R/ W = 1) or write (R/ W = 0) operation is performed. Registers 22 and 23 are read-only.

Table 9. Mode Control Register Map

REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Register 16 R/ W 0 0 1 0 0 0 0 ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0

Register 17 R/ W 0 0 1 0 0 0 1 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

Register 18 R/ W 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE

Register 19 R/ W 0 0 1 0 0 1 1 REV ATS1 ATS0 OPE RSV DFMS FLT INZD

Register 20 R/ W 0 0 1 0 1 0 0 RSV SRST DSD DFTH MONO CHSL OS1 OS0

Register 21 R/ W 0 0 1 0 1 0 1 RSV RSV RSV RSV RSV DZ1 DZ0 PCMZ

Register 22 R 0 0 1 0 1 1 0 RSV RSV RSV RSV RSV RSV ZFGR ZFGL

Register 23 R 0 0 1 0 1 1 1 RSV RSV RSV ID4 ID3 ID2 ID1 ID0

R/ W: Read/Write Mode Select

When R/ W = 0, a write operation is performed.

When R/ W = 1, a read operation is performed.

Default value: 0

ATx[7:0]: Digital Attenuation Level Setting

These bits are available for read and write.

Default value: 1111 1111b

Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to – 120 dB, in

0.5-dB steps. Alternatively, the attenuator can be set to infinite attenuation (or mute). The attenuation data for

each channel can be set individually. However, the data load control (the ATLD bit of control register 18) is

common to both attenuators. ATLD must be set to '1' in order to change an attenuator setting. The attenuation

level can be set using Equation 1 :

Attenuation level (dB) = 0.5 dB × (ATx[7:0]

DEC

– 255)

Where,

ATx[7:0]

DEC

= 0 through 255

For ATx[7:0]

DEC

= 0 through 14, the attenuator is set to infinite attenuation. Table 10 lists the attenuation levels

for various settings.

Product Folder Link(s): PCM1795