Datasheet

Slave Address
MSB LSB
1
0 0
1 1
ADR1
ADR0
R/
W
Packet Protocol
9
SDA
SCL
St
Start
Condition
17 8 18 9 18 9 9 Sp
Stop
Condition
SlaveAddress ACK DATA ACK DATA ACK ACKR/W
ReadOperation
Transmitter
M M M
S S
M
S
M M M
DataType
St SlaveAddress
R
ACK
DATA
ACK
DATA
ACK NACK
Sp
WriteOperation
Transmitter
M M M
S
M
S
M
S S
M
DataType
St SlaveAddress
W
ACK
DATA
ACK
DATA
ACK ACK
Sp
R/ :ReadOperationif1;Otherwise,WriteOperation
ACK:AcknowledgmentofaByteif0
NACK:NotAcknowledgedif1
DATA:8Bits(Byte)
W
M:MasterDevice
S:SlaveDevice
St:StartCondition
Sp:StopCondition
R:Read
:Write
W
ACK:Acknowledge
NACK:NotAcknowledged
PCM1795
SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com
The PCM1795 has seven bits for its own slave address, as shown in Figure 44 . The first five bits (MSBs) of the
slave address are factory preset to 10011. The next two bits of the address byte are the device select bits that
can be user-defined by the ADR1 and ADR0 terminals. A maximum of four PCM1795s can be connected on the
same bus at one time. Each PCM1795 responds when it receives its own slave address.
Figure 44. Slave Address
A master device must control packet protocol that consists of a start condition, slave address, read/write bit, data
if write or acknowledge if read, and stop condition. The PCM1795 supports only slave receivers and slave
transmitters.
Figure 45. Basic I
2
C Framework
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Product Folder Link(s): PCM1795