Datasheet


SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006
www.ti.com
22
I
OUT
–
Figure 25
Circuit
I
OUT
+
I
OUT
L– (Pin 26)
I
OUT
L+ (Pin 25)
OUT+
1
2
3
Balanced Out
I
OUT
–
Figure 25
Circuit
I
OUT
+
I
OUT
R– (Pin 18)
I
OUT
R+ (Pin 17)
OUT–
Figure 26. Measurement Circuit for Monaural Mode
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
DATA
24
23
22
21
20
19
18
17
16
15
5
6
7
8
9
10
11
12
13
14
PCM1794A
BCK
SCK
DGND
V
DD
MUTE
FMT0
FMT1
ZERO
RST
AGND2
I
OUT
R–
V
CC
1
V
COM
L
V
COM
R
I
REF
I
OUT
R+
AGND3R
AGND1
MONO
1
2
3
4
CHSL
DEM
LRCK
28
27
26
25
V
CC
2L
AGND3L
I
OUT
L–
I
OUT
L+
V
CC
2R
DATA
Analog
Output Stage
(See Figure 23)
WDCK
BCK
SCK
External
Filter
Device
V
DD
Figure 27. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application