Datasheet

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SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006
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15
AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the
serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio
interface. Serial data is clocked into the PCM1794A on the rising edge of BCK. LRCK is the serial audio left/right word
clock.
The PCM1794A requires the synchronization of LRCK and the system clock, but does not need a specific phase
relation between LRCK and the system clock.
If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is initialized
within 1/f
S
and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the
system clock is completed.
PCM Audio Data Formats and Timing
The PCM1794A supports industry-standard audio data formats, including standard right-justified, I
2
S, and
left-justified. The data formats are shown in Figure 22. Data formats are selected using the format bits,
FMT1 (pin 12), and FMT0 (pin 11) as shown in Table 2. All formats require binary twos-complement, MSB-first audio
data. Figure 21 shows a detailed timing diagram for the serial audio interface.
DATA
t
(BCH)
50% of V
DD
BCK
LRCK
t
(BCL)
t
(LB)
t
(BCY)
t
(DS)
t
(DH)
50% of V
DD
50% of V
DD
t
(BL)
PARAMETERS MIN MAX UNITS
t
(BCY)
BCK pulse cycle time 70 ns
t
(BCL)
BCK pulse duration, LOW 30 ns
t
(BCH)
BCK pulse duration, HIGH 30 ns
t
(BL)
BCK rising edge to LRCK edge 10 ns
t
(LB)
LRCK edge to BCK rising edge 10 ns
t
(DS)
DATA setup time 10 ns
t
(DH)
DATA hold time 10 ns
— LRCK clock duty 50% ± 2 bit clocks
Figure 21. Timing of Audio Interface