Datasheet
SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006
www.ti.com
13
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The PCM1794A requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 7). The PCM1794A has a system clock detection circuit
that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system
clock frequencies for common audio sampling rates.
Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators
is an excellent choice for providing the PCM1794A system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (f
SCK
) (MHz)
SAMPLING FREQUENCY
128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
32 kHz 4.096 6.144 8.192 12.288 16.384 24.576
44.1 kHz 5.6488 8.4672 11.2896 16.9344 22.5792 33.8688
48 kHz 6.144 9.216 12.288 18.432 24.576 36.864
96 kHz 12.288 18.432 24.576 36.864 49.152 73.728
192 kHz 24.576 36.864 49.152 73.728
(1) (1)
(1)
This system clock rate is not supported for the given sampling frequency.
t
(SCKH)
t
(SCY)
System Clock (SCK)
t
(SCKL)
2 V
0.8 V
H
L
PARAMETERS MIN MAX UNITS
t
(SCY)
System clock pulse cycle time 13 ns
t
(SCKH)
System clock pulse duration, HIGH 0.4 t
(SCY)
ns
t
(SCKL)
System clock pulse duration, LOW 0.4 t
(SCY)
ns
Figure 18. System Clock Input Timing
Power-On and External Reset Functions
The PCM1794A includes a power-on reset function. Figure 19 shows the operation of this function. With V
DD
> 2
V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
V
DD
> 2 V.
The PCM1794A also includes an external reset capability using the RST input (pin 14). This allows an external
controller or master reset circuit to force the PCM1794A to initialize to its default reset state.
Figure 20 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The
RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock
periods. The external reset is especially useful in applications where there is a delay between the PCM1794A power
up and system clock activation.