Datasheet

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006
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42
Pin Assignment When Using DSD Format Interface
Several pins are redefined for DSD mode operation. These include:
D DATA (pin 5): DSDL as L-channel DSD data input
D LRCK (pin 4): DSDR as R-channel DSD data input
D SCK (pin 7): DBCK as bit-clock input
D BCK (pin 6): Set LOW (N/A)
t = 1/(64 × 44.1 kHz)
D1
DSDL
DSDR
D0 D2 D3 D4
DBCK
Figure 44. Normal Data Output Form From DSD Decoder
DSDL
DSDR
t
(BCH)
DBCK
t
(BCL)
t
(BCY)
50% of V
DD
50% of V
DD
t
(DS)
t
(DH)
PARAMETER MIN MAX UNITS
t
(BCY)
DBCK pulse cycle time 85
(1)
ns
t
(BCH)
DBCK high-level time 30 ns
t
(BCL)
DBCK low-level time 30 ns
t
(DS)
DSDL, DSDR setup time 10 ns
t
(DH)
DSDL, DSDR hold time 10 ns
(1)
2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is
specified as a sampling rate of DSD.)
Figure 45. Timing for DSD Audio Interface