Datasheet
SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006
www.ti.com
41
OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection
Default value: 00
OS[1:0]
Operation Speed Select
00 8 times WDCK (default)
01 4 times WDCK
10 16 times WDCK
11 Reserved
The effective oversampling rate is determined by the oversampling performed by both the external digital filter
and the delta-sigma modulator. For example, if the external digital filter is 8× oversampling, and the user selects
OS[1:0] = 00, then the delta-sigma modulator oversamples by 8×, resulting in an effective oversampling rate
of 64×. The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling
rate selected is 16× WDCK, the system clock frequency must be over 256 f
S
.
APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE
Bit Clock
DSD Decoder
DATA
5
6
7
BCK
SCK
ZEROL
1
2
3
4
ZEROR
MSEL
LRCK
PCM1792A
DATA_R
DATA_L
Figure 43. Connection Diagram in DSD Mode
Feature
This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CDt (SACD)
applications.
The DSD mode is accessed by programming the following bit in the corresponding control register.
DSD = 1 (register 20)
The DSD mode provides a low-pass filtering function. The filtering is provided using an analog FIR filter
structure. Four FIR responses are available and are selected by the DMF[1:0] bits of control register 18.
The DSD bit must be set before inputting DSD data; otherwise, the PCM1792A erroneously detects the TDMCA
mode, and commands are not accepted through the serial control interface.
Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.