Datasheet

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SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006
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22
I
2
C Interface
The PCM1792A supports the I
2
C serial bus and the data transmission protocol for standard and fast mode as a slave
device. This protocol is explained in I
2
C specification 2.0.
In I
2
C mode, the control terminals are changed as follows.
TERMINAL NAME TDMCA NAME PROPERTY DESCRIPTION
MS ADR0 Input I
2
C address 0
MDI ADR1 Input I
2
C address 1
MC SCL Input I
2
C clock
MDO SDA Input/output I
2
C data
Slave Address
MSB LSB
1 0 0 1 1 ADR1 ADR0 R/W
The PCM1792A has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset to
10011. The next two bits of the address byte are the device select bits which can be user-defined by the ADR1 and ADR0
terminals. A maximum of four PCM1792As can be connected on the same bus at one time. Each PCM1792A responds
when it receives its own slave address.
Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data if write
or acknowledge if read, and stop condition. The PCM1792A supports only slave receivers and slave transmitters.
9
SDA
SCL St
Start
1−7 8 1−8 9 1−8 9 9 Sp
Stop
Slave Address ACK DATA ACK DATA ACK ACK
Conditio
n
Condition
R/W
R
ead Operation
Transmitter
M M M S S M S M M M
Data Type
St Slave Address R ACK DATA ACK DATA ACK NACK Sp
W
rite Operation
Transmitter
M M M S M S M S S M
Data Type
St Slave Address W ACK DATA ACK DATA ACK ACK Sp
R/W: Read Operation if 1; Otherwise, Write Operation
DATA: 8 Bits (Byte)
ACK: Acknowledgement of a Byte if 0
NACK:Not Acknowledgement if 1
M: Master Device S: Slave Device
St: Start Condition Sp: Stop Condition W: Write R: Read
Figure 32. Basic I
2
C Framework