Datasheet

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SLES071B − MARCH 2003 − REVISED NOVEMBER 2006
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36
APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE
SCK
24
23
22
21
20
19
18
17
16
15
5
6
7
8
9
10
11
12
13
14
PCM1791A
RST
V
DD
DGND
AGNDF
V
CC
R
AGNDR
V
OUT
R–
V
OUT
R+
V
COM
MSEL
V
OUT
L–
ZEROL
ZEROR
V
CC
F
V
CC
L
V
OUT
L+
AGNDC
AGNDL
LRCK
1
2
3
4
BCK
DATA
MUTE
28
27
26
25
MS
MC
MDI
MDO
V
CC
C
Mode
Control
WDCK (Word Clock)
BCK
DATA-L
SCK
Analog
Output Stage
(Same as Standard
Application)
Analog
Output Stage
(Same as Standard
Application)
DF1704
DF1706
PMD200
DATA-R
Figure 38. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application
Application for Interfacing With an External Digital Filter
For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it
can provide improved stop-band attenuation when compared to the internal digital filter of the PCM1791A.
The PCM1791A supports several external digital filters, including:
D Texas Instruments DF1704 and DF1706
D Pacific Microsonics PMD200 HDCD filter/decoder IC
D Programmable digital signal processors
The external digital filter application mode is accessed by programming the following bit in the corresponding control
register:
D DFTH = 1 (register 20)
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of
Figure 38. The word clock (WDCK) signals must be operated at 8× or 4× the desired sampling frequency, f
S
.
Pin Assignments When Using the External Digital Filter Interface
D LRCK (pin 1): WDCK as word clock input
D BCK (pin 2): BCK as bit clock for audio data
D DATA (pin 3): DATAL as L-channel audio data input
D MUTE (pin 4): DATAR as R-channel audio data input