Datasheet
SLES071B − MARCH 2003 − REVISED NOVEMBER 2006
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31
DFTH: Digital Filter Bypass (or Through Mode) Control
This bit is available for read and write.
Default value: 0
DFTH = 0
Digital filter enabled (default)
DFTH = 1 Digital filter bypassed for the external digital filter
The DFTH bit enables or disables the external digital filter interface mode.
MONO: Monaural Mode Selection
This bit is available for read and write.
Default value: 0
MONO = 0 Stereo mode (default)
MONO = 1 Monaural mode
The MONO function changes operation mode from the normal stereo mode to the monaural mode. When the
monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input data. Channel
selection is available for L-channel or R-channel data, determined by the setting of the CHSL bit as described
immediately following.
CHSL: Channel Selection for Monaural Mode
This bit is available for read and write.
Default value: 0
CHSL = 0 L-channel selected (default)
CHSL = 1 R-channel selected
This bit is available when MONO = 1.
The CHSL bit selects L-channel or R-channel data to be used in monaural mode. In the DSD mono mode, DATA (pin
3) is used for the input data.
OS[1:0]: Delta-Sigma Oversampling Rate Selection
These bits are available for read and write.
Default value: 00
OS[1:0] Operation Speed Select
00 64 times f
S
(default)
01 32 times f
S
10 128 times f
S
11 Reserved
The OS bits change the oversampling rate of delta-sigma modulation. Use of this function enables the designer to
stabilize the conditions at the post low-pass filter for different sampling rates. As an application example,
programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation
allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128 f
S
oversampling rate is not
available at sampling rates above 100 kHz. If the 128-f
S
oversampling rate is selected, a system clock of more than
256 f
S
is required.
In DSD mode, these bits select the speed of the bit clock for DSD data coming into the analog FIR filter.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Register 21 R/W 0 0 1 0 1 0 1 RSV RSV RSV RSV RSV DZ1 DZ0 PCMZ
R/W: Read/Write Mode Select
When R/W = 0, a write operaton is performed.
When R/W = 1, a read operaton is performed.
Default value: 0