Datasheet

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SLES071B − MARCH 2003 − REVISED NOVEMBER 2006

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FUNCTION DESCRIPTIONS

Zero Detect

The PCM1791A has a zero-detect function. When the PCM1791A detects the zero conditions as shown in Table 2,

the PCM1791A sets ZEROL (pin 23) and ZEROR (pin 22) to HIGH.

Table 2. Zero Conditions

MODE DETECTING CONDITION AND TIME

PCM DATA is continuously LOW for 1024 LRCKs.

External DF mode DATA is continuously LOW for 1024 WDCKs.

DSD

DZ0 There are an equal number of 1s and 0s in every 8 bits of DSD input data for 23 ms.

DSD

DZ1 The input data is 1001 0110 continuously for 23 ms.

Soft Mute

The PCM1791A supports the mute operation by both hardware and software control. When MUTE (pin 4) is set to

HIGH, or the MUTE bit in mode register 18 is set to 1, both analog outputs are attenuated to the bipolar zero level

in a series of –0.5-dB steps. The duration of the steps is controlled by the setting of the ATS0 and ATS1 bits in mode

Serial Control Interface

The PCM1791A supports SPI and I

C that sets mode control registers as shown in Table 4. The serial control

interface is selected by MSEL (pin 24); SPI is activated when MSEL is set to LOW, and I

C is activated when MSEL

is set to HIGH.

SPI Interface

The SPI interface is a 4-wire synchronous serial port which operates asynchronously to the serial audio interface and

the system clock (SCK). The serial control interface is used to program and read the on-chip mode registers. The

control interface includes MDO (pin 25), MDI (pin 26), MC (pin 27), and MS (pin 28). MDO is the serial data output,

used to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers;

MC is the serial bit clock, used to shift data in and out of the control port, and MS is the mode control enable, used

to enable the internal mode register access.

All read/write operations for the serial control port use 16-bit data words. Figure 29 shows the control data word

format. The most significant bit is the read/write (R/W) bit. For write operations, the R/W bit must be set to 0. For

read operations, the R/W bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or

address) for the read and write operations. The least significant eight bits, D[7:0], contain the data to be written to,

or the data that was read from, the register specified by IDX[6:0].

Figure 30 shows the functional timing diagram for writing or reading the serial control port. MS is held at a logic 1

state until a register needs to be written or read. To start the register write or read cycle, MS is set to logic 0. Sixteen

clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI and readback data

on MDO. After the eighth clock cycle has completed, the data from the indexed-mode control register appears on

MDO during the read operation. After the sixteenth clock cycle has completed, the data is latched into the

indexed-mode control register during the write operation. To write or read subsequent data, MS must be set to 1 once.

MSB

LSB

R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D4D5 D3 D2 D1 D0

Figure 29. Control Data Word Format for MDI