Datasheet

REGISTER DEFINITIONS
PCM1789
SBAS451A – OCTOBER 2008 – REVISED JANUARY 2009 .............................................................................................................................................. www.ti.com
DEC HEX B7 B6 B5 B4 B3 B2 B1 B0
16 10 MRST SRST AMUTE3 AMUTE2 AMUTE1 AMUTE0 SRDA1 SRDA0
MRST Mode control register reset
This bit sets the mode control register reset to the default value. Pop noise may be generated.
Returning the MRST bit to '1' is unnecessary because it is automatically set to '1' after the mode
control register is reset.
Default value = 1.
MRST Mode control register reset
0 Set default value
1 Normal operation (default)
SRST System reset
This bit controls the system reset, which includes the resynchronization between the system
clock and sampling clock, and DAC operation restart. The mode control register is not reset and
the PCM1789 does not go into a power-down state. Returning the SRST bit to '1' is unnecessary;
it is automatically set to '1' after triggering a system reset.
Default value = 1.
SRST System reset
0 Resynchronization
1 Normal operation (default)
AMUTE[3:0] Analog mute function control
These bits control the enabling/disabling of each source event that triggers the analog mute
control circuit.
Default value = 0000.
AMUTE Analog mute function control
xxx0 Disable analog mute control by SCKI halt
xxx1 Enable analog mute control by SCKI halt
xx0x Disable analog mute control by asynchronous detect
xx1x Enable analog mute control by asynchronous detect
x0xx Disable analog mute control by ZERO1 and ZERO2 detect
x1xx Enable analog mute control by ZERO1 and ZERO2 detect
0xxx Disable analog mute control by DAC disable command
1xxx Enable analog mute control by DAC disable command
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