Datasheet

TIMING REQUIREMENTS: SCL AND SDA
t
BUF
t
D-SU
t
D-HD
t
SDA-R
t
SDA-F
t
P-SU
t
SCL-F
t
S-HD
t
LOW
t
SCL-R
t
HI
t
S-SU
t
S-HD
START
Repeated
START
STOP
SDA
SCL
PCM1789
SBAS451A – OCTOBER 2008 – REVISED JANUARY 2009 .............................................................................................................................................. www.ti.com
A detailed timing diagram for SCL and SDA is shown in Figure 36 .
Figure 36. SCL and SDA Control Interface Timing
Table 12. Timing Requirements for Figure 36
STANDARD MODE FAST MODE
SYMBOL PARAMETER MIN MAX MIN MAX UNIT
f
SCL
SCL clock frequency 100 400 kHz
t
BUF
Bus free time between STOP and START condition 4.7 1.3 µ s
t
LOW
Low period of the SCL clock 4.7 1.3 µ s
t
HI
High period of the SCL clock 4.0 0.6 µ s
t
S-SU
Setup time for START/Repeated START condition 4.7 0.6 µ s
t
S-HD
Hold time for START/Repeated START condition 4.0 0.6 µ s
t
D-SU
Data setup time 250 100 ns
t
D-HD
Data hold time 0 3450 0 900 ns
t
SCL-R
Rise time of SCL signal 1000 20 + 0.1 C
B
300 ns
t
SCL-F
Fall time of SCL signal 1000 20 + 0.1 C
B
300 ns
t
SDA-R
Rise time of SDA signal 1000 20 + 0.1 C
B
300 ns
t
SDA-F
Fall time of SDA signal 1000 20 + 0.1 C
B
300 ns
t
P-SU
Setup time for STOP condition 4.0 0.6 µ s
t
GW
Allowable glitch width N/A 50 ns
C
B
Capacitive load for SDA and SCL line 400 100 pF
Noise margin at high level for each connected device
V
NH
0.2 × VDD 0.2 × VDD V
(including hysteresis)
Noise margin at low level for each connected device
V
NL
0.1 × VDD 0.1 × VDD V
(including hysteresis)
V
HYS
Hysteresis of Schmitt trigger input N/A 0.05 × VDD V
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