Datasheet

TIMING REQUIREMENTS
MS
1.4V
1.4V
1.4V
t
MSH
LSB(D0)
t
MSS
t
MCH
t
MCL
t
MDS
ADR0
MSB(R/ )W
MC
MD
t
MDH
t
MCY
t
MHH
D7
TWO-WIRE (I
2
C) SERIAL CONTROL
MSB LSB
1
0 0 1
1
ADR1
ADR0
R/W
PCM1789
SBAS451A – OCTOBER 2008 – REVISED JANUARY 2009 .............................................................................................................................................. www.ti.com
Figure 31 shows a detailed timing diagram for the three-wire serial control interface. These timing parameters are
critical for proper control port operation.
Figure 31. Three-Wire Serial Control Interface Timing
Table 11. Timing Requirements for Figure 31
SYMBOL PARAMETER MIN MAX UNIT
t
MCY
MC pulse cycle time 100 ns
t
MCL
MC low-level time 40 ns
t
MCH
MC high-level time 40 ns
t
MHH
MS high-level time t
MCY
ns
t
MSS
MS falling edge to MC rising edge 30 ns
t
MSH
MS rising edge from MC rising edge for LSB 15 ns
t
MDH
MD hold time 15 ns
t
MDS
MD setup time 15 ns
The PCM1789 supports an I
2
C-compatible serial bus and data transmission protocol for fast mode configured as
a slave device. This protocol is explained in the I
2
C specification 2.0.
The PCM1789 has a 7-bit slave address, as shown in Figure 32 . The first five bits are the most significant bits
(MSBs) of the slave address and are factory-preset to '10011'. The next two bits of the address byte are
selectable bits that can be set by MS/ADR0/RSV and ADR5/ADR1/RSV. A maximum of four PCM1789s can be
connected on the same bus at any one time. Each PCM1789 responds when it receives its own slave address.
Figure 32. Slave Address
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