Datasheet

AMUTE CONTROL
MODE CONTROL
PARALLEL HARDWARE CONTROL
PCM1789
SBAS451A – OCTOBER 2008 – REVISED JANUARY 2009 .............................................................................................................................................. www.ti.com
The PCM1789 has an AMUTE control input, status output pins, and functionality. AMUTEI is the input control pin
of the internal analog mute circuit. An AMUTEI low input causes the DAC output to cut-off from the digital input
and forces it to the center level (0.5 VCC1). AMUTEO is the status output pin of the internal analog mute circuit.
AMUTEO low indicates the analog mute control circuit is active because of a programmed condition (such as an
SCKI halt, asynchronous detect, zero detect, or by the DAC disable command) that forces the DAC outputs to a
center level. Because AMUTEI is not terminated internally and AMUTEO is an open-drain output, pull-ups by the
appropriate resistors are required for proper operation.
Note that the AMUTEO pin is multiplexed with the ZERO2 pin. The desired pin is selected through the MZSEL bit
in control register 22 (16h). The default setting is the selection of the ZERO2 pin.
Additionally, because the AMUTEI pin control and power-down control in register (OPEDA when high, PSMDA
when low) do not function together, AMUTEI takes priority over power-down control. Therefore, power-down
control is ignored during AMUTEI low, and AMUTEI low forces the DAC output to a center level (0.5 VCC1) even
if power-down control is asserted.
The PCM1789 includes three mode control interfaces with three oversampling configurations, depending on the
input state of the MODE pin, as shown in Table 7 . The pull-up and pull-down resistors must be 220 k Ω ± 5%.
Table 7. Interface Mode Control Selection
MODE MODE CONTROL INTERFACE
Tied to DGND Two-wire (I
2
C) serial control, selectable oversampling configuration
Pull-down resistor to DGND Two-wire parallel control, auto mode oversampling configuration
Pull-up resistor to VDD Three-wire (SPI) serial control, selectable oversampling configuration, ADR6 = '0'
Tied to VDD Three-wire (SPI) serial control, selectable oversampling configuration, ADR6 = '1'
The input state of the MODE pin is sampled at the moment of power-on, or during a low-to-high transition of the
RST pin, with the system clock input. Therefore, input changes after reset are ignored until the next power-on or
reset. From the mode control selection described in Table 7 , the functions of four pins are changed, as shown in
Table 8 .
Table 8. Pin Functions for Interface Mode
PIN ASSIGNMENTS
PIN SPI I
2
C H/W
21 MD (input) SDA (input/output) DEMP (input)
22 MC (input) SCL (input) FMT (input)
23 MS (input) ADR0 (input) RSV (input, low)
24 ADR5 (input) ADR1 (input) RSV (input, low)
In serial mode control, the actual mode control is performed by register writes (and reads) through the SPI- or
I
2
C-compatible serial control port. In parallel mode control, two specific functions are controlled directly through
the high/low control of two specific pins, as described in the following section.
The functions shown in Table 9 and Table 10 are controlled by two pins, DEMP and FMT, in parallel hardware
control mode. The DEMP pin controls the 44.1-kHz digital de-emphasis function of both channels. The FMT pin
controls the audio interface format for both channels.
Table 9. DEMP Functionality
DEMP DESCRIPTION
Low De-emphasis off
High 44.1 kHz de-emphasis on
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