Datasheet

SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
Stateof
Synchronization
Synchronous
Normal Normal
Synchronous
Asynchronous
DAC
VOUTx±
VCOM
(0.5VCC1)
Within1/f
S
38/f (single,dualrate)
29/f (quadrate)
S
S
UndefinedData
ZERO FLAG
PCM1789
www.ti.com .............................................................................................................................................. SBAS451A – OCTOBER 2008 – REVISED JANUARY 2009
The PCM1789 operates under the system clock (SCKI) and the audio sampling rate (LRCK). Therefore, SCKI
and LRCK must have a specific relationship. The PCM1789 does not need a specific phase relationship between
the audio interface clocks (LRCK, BCK) and the system clock (SCKI), but does require a specific frequency
relationship (ratiometric) between LRCK, BCK, and SCKI.
If the relationship between SCKI and LRCK changes more than ± 2 BCK clocks because of jitter, sampling
frequency change, etc., the DAC internal operation stops within 1/f
S
, and the analog output is forced into VCOM
(0.5 VCC1) until re-synchronization among SCKI, LRCK, and BCK completes, and then either 38/f
S
(single, dual
rate) or 29/f
S
(quad rate) passes. In the event the change is less than ± 2 BCKs, re-synchronization does not
occur, and this analog output control and discontinuity does not occur.
Figure 28 shows the DAC analog output during loss of synchronization. During undefined data periods, some
noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or
zero) data to normal data creates a discontinuity of data on the analog outputs, which may then generate some
noise in the audio signal.
The DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and
re-synchronization processes will occur after the system clock resumes.
Figure 28. DAC Outputs During Loss of Synchronization
The PCM1789 has two ZERO flag pins (ZERO1 and ZERO2) that can be assigned to the combinations shown in
Table 6 . Zero flag combinations are selected through the AZRO bit in control register 22 (16h). If the input data
of all the assigned channels remain at '0' for 1024 sampling periods (LRCK clock periods), the ZERO1/2 bits are
set to a high level, logic '1' state. Furthermore, if the input data of any of the assigned channels read '1', the
ZERO1/2 are set to a low level, logic '0' state, immediately. Zero data detection is supported for 16-/20-/24-bit
data width, but is not supported for 32-bit data width.
The active polarity of the zero flag output can be inverted through the ZREV bit in control register 22 (16h). The
reset default is active high for zero detection.
In parallel hardware control mode, ZERO1 and ZERO2 are fixed with combination A, shown in Table 6 .
Table 6. Zero Flag Outputs Combination
ZERO FLAG COMBINATION ZERO1 ZERO2
A Left channel Right channel
B Left channel or right channel Left channel and right channel
Note that the ZERO2 pin is multiplexed with AMUTEO pin. Selection of ZERO2 or AMUTEO can be changed
through the MZSEL bit in control register 22 (16h). The default setting after reset is the selection of ZERO2.
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