Datasheet

AUDIO INTERFACE TIMING
t
LRS
1.4V
1.4V
1.4V
BCK
(Input)
LRCK
(Input)
DIN
(Input)
t
BCH
t
BCL
t
BCY
t
LRH
t
DIS
t
DIH
t
LRW
PCM1789
SBAS451A – OCTOBER 2008 – REVISED JANUARY 2009 .............................................................................................................................................. www.ti.com
Figure 27 and Table 5 describe the detailed audio interface timing specifications.
Figure 27. Audio Interface Timing Diagram for Left-Justified, Right-Justified, I
2
S, and DSP Data Formats
Table 5. Timing Requirements for Figure 27
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
BCY
BCK cycle time 75 ns
t
BCH
BCK pulse width high 35 ns
t
BCL
BCK pulse width low 35 ns
LRCK pulse width high (LJ, RJ and I
2
S formats) 1/(2 × f
S
) 1/(2 × f
S
) sec
t
LRW
LRCK pulse width high (DSP format) t
BCY
t
BCY
sec
t
LRS
LRCK setup time to BCK rising edge 10 ns
t
LRH
LRCK hold time to BCK rising edge 10 ns
t
DIS
DIN setup time to BCK rising edge 10 ns
t
DIH
DIN hold time to BCK rising edge 10 ns
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