Datasheet

RESET OPERATION
VDD
0V
0.5 VCC´
(VDD=3.3V,typ)
VCOM
(0.5 VCC1)´
3846 SCKI´
NormalOperation
SynchronousClocks
(VDD=2.2V,typ)
RST
InternalReset
VOUTx±
SCKI,
BCK,
LRCK
VDD
SynchronousClocks
Power-Down
NormalOperationNormalOperation
SynchronousClocks
0V
SCKI,
BCK,
LRCK
RST
InternalReset
VOUTx±
0.5 VCC´
(VDD=3.3V,typ)
3846 SCKI´
100ns(min)
PCM1789
www.ti.com .............................................................................................................................................. SBAS451A – OCTOBER 2008 – REVISED JANUARY 2009
The PCM1789 has both an internal power-on reset circuit and an external reset circuit. The sequences for both
reset circuits are shown in Figure 20 and Figure 21 . Figure 20 illustrates the timing at the internal power-on reset.
Initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is
released after 3846 SCKI clock cycles from power-on, if RST is held high and SCKI is provided. VOUTx from the
DAC is forced to the VCOM level initially (that is, 0.5 × VCC1) and settles at a specified level according to the
rising VCC. If synchronization among SCKI, BCK, and LRCK is maintained, VOUT provides an output that
corresponds to DIN after 3846 SCKI clocks from power-on. If the synchronization is not held, the internal reset is
not released, and both operating modes are maintained at reset and power-down states. After synchronization
forms again, the DAC returns to normal operation with the previous sequences.
Figure 21 illustrates a timing diagram at the external reset. RST accepts an externally-forced reset with RST low,
and provides a device reset and power-down state that achieves the lowest power dissipation state available in
the PCM1789. If RST goes from high to low under synchronization among SCKI, BCK, and LRCK, the internal
reset is asserted, all registers and memory are reset, and finally, the PCM1789 enters into all power-down states.
At the same time, VOUT is immediately forced into the AGND1 level. To begin normal operation again, toggle
RST high; the same power-up sequence is performed as the power-on reset shown in Figure 20 .
The PCM1789 does not require particular power-on sequences for VCC and VDD; it allows VDD on and then
VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings , however,
simultaneous power-on is recommended for avoiding unexpected responses on VOUTx. Figure 20 illustrates the
response for VCC on with VDD on.
Figure 20. Power-On-Reset Timing Requirements
Figure 21. External Reset Timing Requirements
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