Datasheet

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FUNCTIONAL BLOCK DIAGRAM
AIN1L
AIN1R
BCK
DIN
LRCK
MS/ADR
MC/SCL
MD/SDA
MODE
SerialInterface(SPI/I
2
C)
SCKI
DAC
AudioInterface
V
PA
PGND
V
CC
AGND
V
DD
DGND
V
COM
HPOL/
LOL
HPOR/
LOR
6to –70dB
HPL
DAL
DAR
0to –21dB
HPR
LOUT
ROUT
PG5
V
IO
MONO
Clock
Manager
COM
PG1
0/12/20dB
Digital
Filter
6to –70dB
PowerOn
Reset
PowerUp/Down
Manager
0to –21dB
PG6
PG2
0/12/20dB
DAC
Digital
Filter
AnalogInputL
-ch
AnalogInputR
-ch
MXL MXR
V
COM
ModuleofPossiblePowerUp/Down
SW1
SW2 SW3
SW6
SW5 SW4
ATP
DGP
0,6,12,18dB
0to -62dB/Mute
AIN1L
AIN1R
BCK
DIN
LRCK
MS/ADR
MC/SCL
MD/SDA
MODE
SerialInterface(SPI/I
2
C)
SCKI
DS
DAC
AudioInterface
V
PA
PGND
V
CC
AGND
V
DD
DGND
V
COM
HPOL/
LOL
HPOR/
LOR
6to –70dB
HPL
DAL
DAR
0to –21dB
HPR
LOUT
ROUT
PG5
V
IO
MONO
Clock
Manager
COM
PG1
0/12/20dB
Digital
Filter
6to –70dB
PowerOn
Reset
PowerUp/Down
Manager
0to –21dB
PG6
PG2
0/12/20dB
DAC
Digital
Filter
AnalogInputL
-ch
AnalogInputR
-ch
MXL MXR
V
COM
ModuleofPossiblePowerUp/Down
SW1
SW2 SW3
SW6
SW5 SW4
ATP
DGP
0,6,12,18dB
0to -62dB/Mute
DS
PCM1774
SLAS551 – JULY 2007
6
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