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Three-Wire Interface (SPI) Timing Requirements
t
w(MCH)
50%ofV
IO
MS
t
(MLS)
LSB
50%ofV
IO
50%ofV
IO
t
w(MCL)
t
w(MHH)
t
(MLH)
t
(MCY)
t
(MDH)
t
(MDS)
MC
MD
T0013-08
TWO-WIRE INTERFACE [I
2
C, MODE (PIN 28) = HIGH]
SLAVE ADDRESS
PCM1774
SLAS551 – JULY 2007
Figure 19 shows a detailed timing diagram for the serial control interface. These timing parameters are critical
for proper control port operation.
PARAMETERS MIN TYP MAX UNIT
t
(MCY)
MC pulse cycle time 500
(1)
ns
t
w(MCL)
MC low level time 50 ns
t
w(MCH)
MC high level time 50 ns
t
w(MHH)
MS high level time See
(1)
ns
t
(MLS)
MS falling edge to MC rising edge 50 ns
t
(MLH)
MS hold time 20 ns
t
(MDH)
MD hold time 15 ns
t
(MDS)
MD setup time 20 ns
(1) 3/(128 f
S
) s (min), where f
S
is sampling rate.
Figure 19. SPI Interface Timing
The PCM1774 supports the I
2
C serial bus and the data transmission protocol for the I
2
C standard as a slave
device. This protocol is explained in I
2
C specification 2.0.
In I
2
C mode, the control terminals are changed as follows.
TERMINAL NAME PROPERTY DESCRIPTION
MS/ADR Input I
2
C address
MD/SDA Input/output I
2
C data
MC/SCL Input I
2
C clock
MSB LSB
1 0 0 0 1 1 ADR R/ W
The PCM1774 has its own 7-bit slave address. The first six bits (MSBs) of the slave address are factory preset
to 100011. The last bit of the address byte is the device select bit, which can be user-defined by the ADR
terminal. A maximum of two PCM1774 can be connected on the same bus at one time. The PCM1774 responds
when it receives its own slave address.
20
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