Datasheet

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DIN
BCK
(Output)
LRCK
(Output)
50%ofV
IO
SCKI
t
(SCY)
t
(DL)
50%ofV
IO
50%ofV
IO
50%ofV
IO
t
w(BCH)
t
w(BCL)
t
(DB)
t
(DB)
t
(BCY)
t
(DH)
t
(DS)
PCM1774
SLAS551 – JULY 2007
PARAMETERS MIN MAX UNIT
t
(SCY)
SCKI pulse cycle time 1/(256 f
S
)
(1)
t
(DL)
LRCK edge from SCKI rising edge 0 40 ns
t
(DB)
BCK edge from SCKI rising edge 0 40 ns
t
(BCY)
BCK pulse cycle time 1/(64 f
S
)
(1)
t
w(BCH)
BCK high level time 146 ns
t
w(BCL)
BCK low level time 146 ns
t
(DS)
DATA setup time 10 ns
t
(DH)
DATA hold time 10 ns
(1) f
S
is up to 48 kHz. f
S
is the sampling frequency.
Figure 15. Audio Interface Timing (Master Mode)
17
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