Datasheet

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Audio Serial Interface
PCM1774
SLAS551 – JULY 2007
Table 5. Power Consumption Table (continued)
OPERATION MODE CONDITION V
OL
POWER SUPPLY CURRENT [mA] PD [mW]
[V]
V
IO
V
DD
V
CC
V
PA
TOTAL
Zero Data 1.8 0 0 – – 0.0
f
S
= 44.1 kHz
2.8 0 0 – – 0.0
R
L
= 16 Ω
3.3 0 0 – – 0.0
No Digital Input
(1)
Headphone Output with Stereo
Analog Mixing
2.4 – – 0.68 0.38 2.5
2.8 – – 0.69 0.41 3.1
3.3 – – 0.71 0.46 3.9
Zero Data 1.8 0 0 – – 0.0
f
S
= 44.1 kHz
2.8 0 0 – – 0.0
R
L
= 16 Ω
3.3 0 0 – – 0.0
No Digital Input
(1)
Headphone Output with Mono
Analog Mixing
2.4 – – 0.52 0.38 2.2
2.8 – – 0.54 0.42 2.7
3.3 – – 0.55 0.46 3.3
(1) All digital inputs are held static.
The audio serial interface for the PCM1774 comprises LRCK, BCK, DIN, and DOUT. Sampling rate (f
S
), left and
right channel are present on LRCK. DIN receives the serial data for the DAC interpolation filter, and DOUT
transmits the serial data from the ADC decimation filter. BCK clocks the transfer of serial audio data on DIN and
DOUT in its high-to-low transition. BCK and LRCK should be synchronized with audio system clock. Ideally, it is
recommended that they be derived from it.
The PCM1774 requires LRCK to be synchronized with the system clock. The PCM1774 does not require a
specific phase relationship between LRCK and the system clock.
The PCM1774 has both master mode and slave mode interface formats, which can be selected by register 84
(MSTR). In master mode, the PCM1774 generates LRCK and BCK from the system clock.
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