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FEATURES

APPLICATIONS

DESCRIPTION

PCM1774

SLAS551 – JULY 2007

16-Bit, Low-Power Stereo Audio DAC With Analog Mixing, Line and Headphone Outputs

• 2 ( I

C™) or 3 (SPI) Wire Serial Control

• Analog Front End: • Programmable Function by Register Control:

– Stereo Single-Ended Input – Digital Attenuation: 0 dB to –62 dB

– Microphone Amplifier (12 dB, 20 dB) – Digital Gain of DAC: 0, 6, 12, 18 dB

• Analog Back End: – Power Up/Down Control for Each Module

– Stereo/Mono Line Output With Volume – 6-dB to –70-dB Gain for Analog Outputs

– Stereo/Mono Headphone Amplifier With – 0/12/20 dB for Microphone Input

Volume

– 0-dB to –21-dB Gain for Analog Mixing

• Analog Performance:

– Three-Band Tone Control and 3D Sound

– Dynamic Range: 93 dB

– Analog Mixing Control

– 40-mW + 40-mW Headphone Output at

• Pop-Noise Reduction Circuit

= 16 Ω

• Short Protection Circuit

• Power Supply Voltage

• Package: 4-mm × 4-mm QFN Package

– 1.71 V to 3.6 V for Digital I/O Section

• Operation Temperature Range: –40 ° C to 85 ° C

– 1.71 V to 3.6 V for Digital Core Section

– 2.4 V to 3.6 V for Analog Section

• Portable Audio Player, Cellular Phone

– 2.4 V to 3.6 V for Power Amplifier Section

• Video Camcorder, Digital Still Camera

• Low Power Dissipation:

• PMP/DMB/PND

– 6.4 mW in Playback, 1.8 V/2.4 V, 44.1 kHz

– 3.3 μ W in Power Down

• Sampling Frequency: 5 kHz to 50 kHz

The PCM1774 is a low-power stereo DAC designed

• Operation From a Single Clock Input Without

for portable digital audio applications. The device

PLL

integrates headphone amplifier, line amplifier, line

• System Clock:

input, boost amplifier, programmable gain control,

analog mixing, and sound effects. It is available in a

– Common-Audio Clock (256 f

/384 f

), 12/24,

small-footprint, 4-mm × 4-mm QFN package. The

13/26, 13.5/27, 19.2/38.4, 19.68/39.36 MHz

PCM1774 supports right-justified, left-justified, I

and DSP formats, providing easy interfacing to audio

DSP and decoder/encoder chips. Sampling rates up

to 50 kHz are supported. The user-programmable

functions are accessible through a two- or three-wire

serial control port.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

I2C is a trademark of Philips Electronics.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (50 pages)

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PCM1774 SLAS551 – JULY 2007 16-Bit, Low-Power Stereo Audio DAC With Analog Mixing, Line and Headphone Outputs FEATURES • • • • • • • • Analog Front End: – Stereo Single-Ended Input – Microphone Amplifier (12 dB, 20 dB) Analog Back End: – Stereo/Mono Line Output With Volume – Stereo/Mono Headphone Amplifier With Volume Analog Performance: – Dynamic Range: 93 dB – 40-mW + 40-mW Headphone Output at RL = 16 Ω Power Supply Voltage – 1.71 V to 3.
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PCM1774 www.ti.com SLAS551 – JULY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM1774 www.ti.com SLAS551 – JULY 2007 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data (unless otherwise noted).
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PCM1774 www.ti.com SLAS551 – JULY 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data (unless otherwise noted).
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PCM1774 www.ti.com SLAS551 – JULY 2007 PIN ASSIGNMENTS 15 14 13 12 LRCK PGND VPA HPOR/LOR HPOL/LOL PCM1774RGP (TOP VIEW) 11 17 9 SCKI VCC 18 8 DGND AIN1R 19 7 VDD AIN1L 20 6 VIO 1 2 3 4 5 DIN AGND MC/SCL BCK MD/SDA 10 MS/ADR 16 MODE VCOM Table 1. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO.
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Submit Documentation Feedback VCOM AIN1R AIN1L VCOM Power On Reset COM PG5 PG6 VIO 0 to -62dB / Mute 0, 6, 12, 18 dB VDD DGND Analog Input R-ch 0/12/20dB 0 to –21dB PG2 LRCK DIN VPA VCC DS DAC Digital Filter PGND DS DAC AGND DAR DAL SW4 SW5 SW6 SW3 SW2 SW1 MXR MXL ROUT MONO LOUT MODE Serial Interface (SPI/I2C) MD/SDA MC/SCL MS/ADR Digital Filter ATP DGP Audio Interface BCK Analog Input L-ch Clock Manager 0/12/20dB 0 to –21dB PG1 Power Up/Down Manager SCKI
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PCM1774 www.ti.com SLAS551 – JULY 2007 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted. INTERPOLATION FILTER, STOP BAND INTERPOLATION FILTER, PASS BAND 0.2 0 -20 0.1 Amplitude - dB Amplitude - dB -40 -60 0 -80 -0.1 -100 -120 0 -0.2 1 2 f - Frequency - xfs 3 4 0 0.1 0.2 0.3 f - Frequency - xfs 0.4 Figure 1. Figure 2.
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PCM1774 www.ti.com SLAS551 – JULY 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted. THREE-BAND TONE CONTROL (MIDRANGE) THREE-BAND TONE CONTROL (TREBLE) Figure 5. Figure 6. THD+N/SNR vs POWER SUPPLY DAC TO HEADPHONE OUTPUT, 16-Ω THD+N/SNR vs POWER SUPPLY DAC TO LINE OUTPUT, 10-kΩ 93 0.02 92 SNR 91 0.01 90 0 2 2.5 3 3.5 4 fIN = 1 kHz 94 0.011 SNR 0.
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PCM1774 www.ti.com SLAS551 – JULY 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted. OUTPUT POWER vs POWER SUPPLY (HEADPHONE, 16-Ω) THD+N vs OUTPUT POWER (HEADPHONE, 16-Ω, VOLUME = 6 dB) 100 120 THD+N - Total Harmanic Distortion + Noise - % fIN= 1 kHz 100 PO - Output Power - mW Vol = 6 dB 80 60 Vol = 0 dB 40 20 2.5 3 Power Supply - V 3.5 4 3.6 V 2.7 V 1 0.
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PCM1774 www.ti.com SLAS551 – JULY 2007 DETAILED DESCRIPTION Analog Input The AIN1L and AIN1R pins can be used as microphone or line inputs with selectable 0-, 12-, or 20-dB boost and 1-Vrms input. All of these analog inputs have high input impedance (20 kΩ), which is not changed by gain settings. One pair of inputs is selected by register 87 (AIL0 and AIR0).
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PCM1774 www.ti.com SLAS551 – JULY 2007 3-D Sound A 3-D sound effect is provided by mixing L-channel and R-channel data with a band-pass filter with two parameters, mixing ratio and band pass filter characteristic, that can be controlled by register 95 (3DP[3:0], 3FLO). Three-Band Tone Control Tone control has bass, midrange, and treble controls that can be adjusted from 12 dB to –12 dB in 1-dB steps by registers 92 to 94 (LGA[4:0], MGA[4:0] and HGA[4:0]).
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PCM1774 www.ti.com SLAS551 – JULY 2007 DESCRIPTION OF OPERATION System Clock Input The PCM1774 can accept clocks of various frequencies without a PLL. They are used for clocking the digital filters and automatic level control and delta-sigma modulators and are classified as common-audio and application-specific clocks. Table 2 shows frequencies of the common-audio clock and application-specific clock. Figure 13 shows the timing requirements for system clock inputs.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Table 3.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Table 5. Power Consumption Table OPERATION MODE CONDITION VOL [V] VIO VDD VCC VPA TOTAL Zero Data fS = 44.1 kHz RL = 0 Ω 1.8 0.000 0.000 – – 0.000 2.8 0.000 0.000 – – 0.000 3.3 0.000 0.000 – – 0.000 2.4 – – 0.001 0.000 0.002 2.8 – – 0.001 0.000 0.003 3.3 – – 0.001 0.000 0.003 1.8 0 0.84 – – 1.5 2.8 0.03 1.47 – – 4.2 3.3 0.04 1.84 – – 6.2 2.4 – – 1.68 0.38 4.9 2.8 – – 1.81 0.41 6.2 3.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Table 5. Power Consumption Table (continued) OPERATION MODE Headphone Output with Stereo Analog Mixing Headphone Output with Mono Analog Mixing (1) CONDITION VOL [V] VIO VDD VCC VPA TOTAL Zero Data fS = 44.1 kHz RL = 16 Ω No Digital Input (1) 1.8 0 0 – – 0.0 2.8 0 0 – – 0.0 3.3 0 0 – – 0.0 2.4 – – 0.68 0.38 2.5 2.8 – – 0.69 0.41 3.1 3.3 – – 0.71 0.46 3.9 1.8 0 0 – – 0.0 2.8 0 0 – – 0.0 3.3 0 0 – – 0.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Audio Data Formats and Timing The PCM1774 supports I2S, right-justified, left-justified, and DSP formats. The data formats are shown in Figure 16 and are selected using registers 70 and 81 (RFM[1:0], PFM[1:0]). All formats require binary 2s-complement, MSB-first audio data. The default format is I2S. Figure 14 shows a detailed timing diagram.
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PCM1774 www.ti.com SLAS551 – JULY 2007 THREE-WIRE INTERFACE (SPI, MODE (PIN 28) = LOW) All write operations for the serial control port use 16-bit data words. Figure 17 shows the control data word format. The most-significant bit must be 0. There are seven bits, labeled IDX[6:0], that set the register address for the write operation. The least-significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].
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PCM1774 www.ti.com SLAS551 – JULY 2007 Three-Wire Interface (SPI) Timing Requirements Figure 19 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper control port operation.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Packet Protocol The master device must control packet protocol, which consists of start condition, slave address with read/write bit, data (if write) or acknowledgment (if read), and stop condition. The PCM1774 supports only slave receiver and slave transmitter.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Transmitter M M M S M S M M M S Data Type St Slave Address W ACK Reg Address ACK Sr Slave Address R ACK S M M Read Data NACK Sp M: Master Device S: Slave Device St: Start Condition Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge W: Write R: Read R0002-02 NOTE: The slave address after the repeated start condition must be the same as the previous slave address. Figure 22.
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PCM1774 www.ti.com SLAS551 – JULY 2007 USER-PROGRAMMABLE MODE CONTROLS Register Map The mode control register map is shown in Table 6. Each register includes an index (or address) indicated by the IDX[6:0] bits. Table 6.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Register 70 Register 70 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 DEM1 DEM0 PFM1 PFM0 SPX1 SPX0 RSV OVER IDX[6:0]: 100 0110b (46h): Register 70 DEM[1:0]: De-Emphasis Filter Selection Default value: 00 A digital de-emphasis filter is in front of the interpolation filter. One of three de-emphasis filters can be selected corresponding to the sampling rate, 32 kHz, 44.1 kHz, or 48 kHz.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Register 72 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV PMXR PMXL Register 72 IDX[6:0]: 100 1000b (48h) Register 72 PMXR: Power Up/Down for MXR (Mixer R-Channel) PMXL: Power Up/Down for MXL (Mixer L-Channel) Default value: 0 These bits are used to control power up/down for the analog mixer.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Register 74 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV HPS1 HPS0 RSV PCOM Register 74 IDX[6:0]: 100 1010b (4Ah): Register 74 HPS[1:0]: Line or Headphone Output Configuration Default value: 00 HPOL/LOL and HPOR/LOR can be configured selected as follows.
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PCM1774 www.ti.com SLAS551 – JULY 2007 LRPC: LRCK Polarity Control Default value: 0 This bit is used to reverse L-channel and R-channel audio data. LRPC = 0 Normal (default) LRPC = 1 Reverse NPR[5:0]: System Clock Rate Selection Default value: 000000 MSR[2:0]: System Clock Dividing Rate Selection in Master Mode (Register 70) Default value: 000 These bits are used to select the system clock rate and the dividing rate of the input system clock. See Table 9 for the details.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Table 9. System Clock Frequency for Common-Audio Clock SYSTEM CLOCK SCK (MHz) ADC SAMPLING RATE ADC fS (kHz) 6.144 8.192 12.288 18.432 5.6448 11.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Table 10. System Clock Frequency for Application-Specific Clock SYSTEM CLOCK SCK (MHz) 13.5 27 12 24 19.2 32 ADC SAMPLING RATE ADC fS (kHz) DAC SAMPLING RATE DAC fS (kHz) REGISTER SETTINGS MSR[2:0] NPR[5:0] BIT CLOCK BCK (fS) 48.214 (SCK/280) 010 00 0010 70 44.407 (SCK/304) 010 00 0001 76 32.142 (SCK/420) 010 10 0010 70 24.107 (SCK/560) 100 00 0010 70 22.203 (SCK/608) 100 00 0001 76 16.071 (SCK/840) 100 10 0010 70 12.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Table 10. System Clock Frequency for Application-Specific Clock (continued) SYSTEM CLOCK SCK (MHz) 38.4 13 26 19.68 39.36 ADC SAMPLING RATE ADC fS (kHz) DAC SAMPLING RATE DAC fS (kHz) MSR[2:0] NPR[5:0] BIT CLOCK BCK (fS) 48.484 (SCK/792) 011 01 0110 66 44.444 (SCK/864) 011 01 0101 72 32.323 (SCK/1188) 011 11 0110 66 24.242 (SCK/1584) 101 01 0110 66 22.222 (SCK/1728) 101 01 0101 72 16.161 (SCK/2376) 101 11 0110 66 12.
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PCM1774 www.ti.com SLAS551 – JULY 2007 MBST: BCK Output Configuration in Master Mode Default value: 0 This bit is used to control the BCK output configuration in master mode. In master mode, this bit sets the BCK output configuration to normal mode or burst mode. In normal mode (MBST = 0), the BCK clock runs continuously. In burst mode (MBST = 1), the BCK clock runs intermittently, and the number of clock cycles per LRCK period is reduced to equal the number of bits of audio data being transmitted.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Register 88 Register 88 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV MXR2 MXR1 MXR0 RSV MXL2 MXL1 MXL0 IDX[6:0]: 101 1000b (58h): Register 88 MXR2: Mixing SW6 to MXR (R-Channel Mixing Amplifier) From L-Channel Analog Input Default value: 0 This bit is used to mix the analog source into MXR (R-ch mixing amplifier) from the L-ch analog input.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Register 92 Register 92 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 LPAE RSV RSV LGA4 LGA3 LGA2 LGA1 LGA0 IDX[6:0]: 101 1100b (5Ch): Register 92 LPAE: Gain Adjustment for Bass Boost Gain Control Default value: 0 A gain setting for bass boost may cause digital data saturation, depending on the input data level.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Register 93 Register 93 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV MGA4 MGA3 MGA2 MGA1 MGA0 IDX[6:0]: 101 1101b (5Dh): Register 93 MGA[4:0]: Middle Boost Gain Control Default value: 0 0000 These bits are used to set the midrange boost gain level for the digital data. The detailed characteristics are shown in the Typical Performance Curves.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Register 95 Register 95 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV 3DEN RSV 3FL0 3DP3 3DP2 3DP1 3DP0 IDX[6:0]: 101 1111b (5Fh): Register 95 3DEN: 3-D Sound Effect Enable Default value: 0 This bit is used for enabling the 3-D sound effect filter. This filter has two independently controlled parameters.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Register 96 Register 96 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV RSV MXEN IDX[6:0]: 110 0000b (60h): Register 96 MXEN: Digital Monaural Mixing Default value: 0 This bit is used to enable or disable monaural mixing in the section that combines L-ch data and R-ch data.
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PCM1774 www.ti.com SLAS551 – JULY 2007 Register 125 Register 125 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV PTM1 PTM0 RES4 RES3 RES2 RES1 RES0 IDX[6:0]: 111 1101b (7Dh): Register 125 PTM[1:0]: Power-Up/Down Time Control Default value: 00 RES[4:0]: Resister Value Control Default value: 1 1100 These bits are used to optimize audible pop noise and ramp up time for headphone output at device power on/off. Table 11.
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PCM1774 www.ti.com SLAS551 – JULY 2007 CONNECTION DIAGRAMS To Regulator 9 10 11 SCKI VIO BCK VDD LRCK DIN 5 DGND VCC 2 3 4 MODE C1 C2 VPA MC/SCL 1 Pull Down or Up AGND MS/ADR MD/SDA PCM1774 PGND 6 7 C4 C5 8 18 C6 17 13 12 C7 20 AIN1L 19 AIN1R VCOM 16 C8 15 HPOL/LOL C3 14 HPOR/LOR Stereo Headphone C9 Figure 24. Connection Diagram Table 12. Recommended External Parts C1–C2 1–4.7 μF C4 0.1 μF C5, C6, C7 C8, C9 HPOL + 1 μF C3 1–4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM1774RGPR QFN RGP 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 PCM1774RGPR QFN RGP 20 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 PCM1774RGPT QFN RGP 20 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1774RGPR QFN RGP 20 3000 367.0 367.0 35.0 PCM1774RGPR QFN RGP 20 3000 367.0 367.0 35.0 PCM1774RGPT QFN RGP 20 250 210.0 185.0 35.0 PCM1774RGPT QFN RGP 20 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.