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Control Interface Timing Requirements (PCM1772)
t
(MCH)
50% of V
CC1
MS
t
(MLS)
LSB
50% of V
CC1
50% of V
CC1
t
(MCL)
t
(MHH)
t
(MLH)
t
(MCY)
t
(MDH)
t
(MDS)
MC
MD
T0013-01
PCM1772 , PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
Figure 27 shows a detailed timing diagram for the serial control interface. These timing parameters are critical
for proper control port operation.
PARAMETERS SYMBOL MIN TYP MAX UNIT
MC pulse cycle time t
(MCY)
100
(1)
ns
MC low-level time t
(MCL)
50 ns
MC high-level time t
(MCH)
50 ns
MS high-level time t
(MHH)
(2)
ns
MS falling edge to MC rising edge t
(MLS)
20 ns
MS hold time t
(MLH)
20 ns
MD hold time t
(MDH)
15 ns
MD setup time t
(MDS)
20 ns
(1) When MC runs continuously between transactions, MC pulse cycle time is specified as 3/(128 f
S
), where f
S
is the
sampling rate.
(2) 3/(128f
S
) s (minimum), where f
S
is sampling rate
Figure 27. Control Interface Timing
22
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