Datasheet

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t
(DL)
t
(BCY)
t
(SCY)
t
(DS)
50% of V
CC1
LRCK (Output)
50% of V
CC1
50% of V
CC1
50% of V
CC1
SCKI
BCK (Output)
DATA
t
(DH)
t
(BCH)
t
(BCL)
t
(DB)
t
(DB)
T0011-01
PCM1772 , PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
PARAMETERS SYMBOL MIN MAX UNIT
SCKI pulse cycle time t
(SCY)
1/(256 f
S
)
(1)
LRCK edge from SCKI rising edge t
(DL)
0 40 ns
BCK edge from SCKI rising edge t
(DB)
0 40 ns
BCK pulse cycle time t
(BCY)
1/(64 f
S
)
(1)
BCK high-level time t
(BCH)
146 ns
BCK low-level time t
(BCL)
146 ns
DATA setup time t
(DS)
10 ns
DATA hold time t
(DH)
10 ns
(1) f
S
is up to 48 kHz. f
S
is the sampling frequency.
Figure 24. Audio Interface Timing (Master Mode)
19
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