Datasheet

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t
(BCH)
DATA
t
(BCL)
t
(LB)
t
(BCY)
t
(BL)
t
(DH)
t
(DS)
50% of V
CC1
50% of V
CC1
50% of V
CC1
LRCK (Input)
BCK (Input)
T0010-01
PCM1772 , PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
PARAMETERS SYMBOL MIN MAX UNIT
BCK pulse cycle time t
(BCY)
1/(64 f
S
)
(1)
BCK high-level time t
(BCH)
35 ns
BCK low-level time t
(BCL)
35 ns
BCK rising edge to LRCK edge t
(BL)
10 ns
LRCK edge to BCK rising edge t
(LB)
10 ns
DATA setup time t
(DS)
10 ns
DATA hold time t
(DH)
10 ns
(1) f
S
is the sampling frequency.
Figure 23. Audio Interface Timing (Slave Mode)
18
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