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Power On/Off and Reset
V
CC1
, V
CC2
0 V
LRCK, BCK, SCKI
PD
Internal Reset
V
OUT
L, V
OUT
R
1024 Internal System Clocks
9334/f
S
0 V
1 ms (Min)
1 ms (Min)
T0006-01
V
CC1
, V
CC2
0 V
LRCK, BCK, SCKI
PD
V
OUT
L, V
OUT
R
0 V
9334/f
S
T0007-01
PCM1772 , PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
The PCM1772/73 always must have the PD pin set from LOW to HIGH once after power-supply voltages V
CC1
and V
CC2
have reached the specified voltage range and stable clocks SCKI, BCK, and LRCK are being supplied
for the power-on sequence. A minimum time of 1 ms after both the clock and power-supply requirements are
met is required before the PD pin changes from LOW to HIGH, as shown in Figure 19 . Subsequent to the PD
LOW-to-HIGH transition, the internal logic state is held in reset for 1024 system clock cycles prior to the start of
the power-on sequence. During the power-on sequence, V
OUT
L and V
OUT
R increase gradually from ground level,
reaching an output level that corresponds to the input data after a period of 9334/f
S
. When powering off, the PD
pin is set from HIGH to LOW first. Then V
OUT
L and V
OUT
R decrease gradually to ground level over a period of
9334/f
S
, as shown in Figure 20 , after which power can be removed without creating pop noise. When powering
on or off, adhering to the timing requirements of Figure 19 and Figure 20 ensures that pop noise does not occur.
If the timing requirements are not met, pop noise might occur.
Figure 19. Power-On Sequence
Figure 20. Power-Off Sequence
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