Datasheet

www.ti.com
DETAILED DESCRIPTION
System Clock, Reset, and Functions
System Clock Input
t
(SCKH)
t
(SCKY)
SCKI
t
(SCKL)
0.7 V
CC1
0.3 V
CC1
T0005-01
PCM1772 , PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
The PCM1772 and PCM1773 devices require a system clock for operating the digital interpolation filters and
multilevel ∆ - Σ modulators. The system clock is applied at terminal 16 (SCKI). Table 1 shows examples of system
clock frequencies for common audio sampling rates.
Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise.
Table 1. System Clock Frequency for Common Audio Sampling Frequencies
SAMPLING FREQUENCY, LRCK SYSTEM CLOCK FREQUENCY, SCKI (MHz)
128 f
S
192 f
S
256 f
S
384 f
S
48 kHz 6.144 9.216 12.288 18.432
44.1 kHz 5.6448 8.4672 11.2896 16.9344
32 kHz 4.096 6.144 8.192 12.288
24 kHz 3.072 4.608 6.144 9.216
22.05 kHz 2.8224 4.2336 5.6448 8.4672
16 kHz 2.048 3.072 4.096 6.144
12 kHz 1.536 2.304 3.072 4.608
11.025 kHz 1.4112 2.1168 2.8224 4.2336
8 kHz 1.024 1.536 2.048 3.072
SYMBOL PARAMETER MIN UNIT
t
(SCKH)
System clock pulse duration, HIGH 7 ns
t
(SCKL)
System clock pulse duration, LOW 7 ns
t
(SCKY)
System clock pulse cycle time
(1)
52 ns
(1) 1/(128 f
S
), 1/(192 f
S
), 1/(256 f
S
) or 1/(384 f
S
)
Figure 18. System Clock Timing
13
Submit Documentation Feedback