Datasheet

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TERMINAL FUNCTIONS
PCM1772 , PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
PCM1772PW
TERMINAL
I/O DESCRIPTION
NAME NO.
AGND1 5 — Analog ground. This is a return for V
CC1
.
AGND2 6 — Analog ground. This is a return for V
CC2
.
AIN 10 I Monaural analog signal mixer input. The signal can be mixed with the output of the L- and R-channel DACs.
BCK 3 I/O Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is
input from an external device. In master interface mode, the PCM1772 device generates the BCK output to an
external device.
DATA 2 I Serial audio data input
LRCK 1 I/O Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of
LRCK must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an
external device. In the master interface mode, the PCM1772 device generates the LRCK output to an external
device.
MC 14 I Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.
MD 13 I Mode control port serial data input. Controls the operation mode on the PCM1772 device.
MS 15 I Mode control port select. The control port is active when this terminal is low.
PD 4 I Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default
settings.
SCKI 16 I System clock input
V
CC1
12 — Power supply for all analog circuits except the lineout amplifier.
V
CC2
11 — Analog power supply for the lineout amplifier circuits. The voltage level must be the same as V
CC1
.
V
COM
7 — Decoupling capacitor connection. An external 10- µ F capacitor connected from this terminal to analog ground is
required for noise filtering. Voltage level of this terminal is 0.5 V
CC2
nominal.
V
OUT
L 9 O L-channel analog signal output of the lineout amplifiers
V
OUT
R 8 O R-channel analog signal output of the lineout amplifiers
5
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