Datasheet

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T0010-02
t
(BCH)
DATA
t
(BCL)
t
(LB)
t
(BCY)
t
(BL)
t
(DH)
t
(DS)
50% of V
CC
50% of V
CC
50% of V
CC
LRCK (Input)
BCK (Input)
PCM1770 , PCM1771
SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007
PARAMETER MIN MAX UNIT
t
(BCY)
BCK pulse cycle time 1/(64 f
S
)
(1)
t
(BCH)
BCK high-level time 35 ns
t
(BCL)
BCK low-level time 35 ns
t
(BL)
BCK rising edge to LRCK edge 10 ns
t
(LB)
LRCK edge to BCK rising edge 10 ns
t
(DS)
DATA set-up time 10 ns
t
(DH)
DATA hold time 10 ns
(1) f
S
is the sampling frequency.
Figure 23. Audio Interface Timing (Slave Mode)
19
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