Datasheet

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T0011-02
t
(DL)
t
(BCY)
t
(SCY)
t
(DS)
50% of V
CC
LRCK (Output)
50% of V
CC
50% of V
CC
50% of V
CC
SCKI
BCK (Output)
DATA
t
(DH)
t
(BCH)
t
(BCL)
t
(DB)
t
(DB)
PCM1770 , PCM1771
SLES011E – SEPTEMBER 2001 – REVISED MARCH 2007
PARAMETER MIN MAX UNIT
t
(SCY)
SCKI pulse cycle time 1/(256 f
S
)
(1)
t
(DL)
LRCK edge from SCKI rising edge 0 40 ns
t
(DB)
BCK edge from SCKI rising edge 0 40 ns
t
(BCY)
BCK pulse cycle time 1/(64 f
S
)
(1)
t
(BCH)
BCK high-level time 146 ns
t
(BCL)
BCK low-level time 146 ns
t
(DS)
DATA setup time 10 ns
t
(DH)
DATA hold time 10 ns
(1) f
S
is up to 48 kHz. f
S
is the sampling frequency.
Figure 24. Audio Interface Timing (Master Mode)
20
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