Datasheet

PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
www.ti.com
12
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The PCM1753/54/55 requires a system clock for operating the digital interpolation filters and multilevel
delta-sigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 shows examples of
system clock frequencies for common audio sampling rates.
Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important
to use a clock source with low phase-jitter and noise. TI’s PLL170x family of multiclock generators is an excellent
choice for providing the PCM1753/54/55 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)
SAMPLING FREQUENCY
128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
1152 f
S
8 kHz 1.0240 1.5360 2.0480 3.0720 4.0960 6.1440 9.2160
16 kHz 2.0480 3.0720 4.0960 6.1440 8.1920 12.2880 18.4320
32 kHz 4.0960 6.1440 8.1920 12.2880 16.3840 24.5760 36.8640
44.1 kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 (1)
48 kHz 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 (1)
88.2 kHz 11.2896 16.9344 22.5792 33.8688 45.1584 (1) (1)
96 kHz 12.2880 18.4320 24.5760 36.8640 49.1520 (1) (1)
192 kHz 24.5760 36.8640 (1) (1) (1) (1) (1)
(1)
This system clock rate is not supported for the given sampling frequency.
t
(SCKH)
t
(SCY)
System Clock (SCK)
t
(SCKL)
2.0 V
0.8 V
H
L
PARAMETERS SYMBOL MIN TYP MAX UNITS
System clock pulse duration, high t
(SCKH)
7 ns
System clock pulse duration, low t
(SCKL)
7 ns
System clock pulse cycle time t
(SCY)
(1)
ns
(1)
1/128 f
S
, 1/256 f
S
, 1/384 f
S
, 1/512 f
S
, 1/768 f
S
, or 1/1152 f
S
Figure 19. System Clock Input Timing