Datasheet

PCM1753
PCM1754
PCM1755
SLES092C – OCTOBER 2003 – REVISED FEBRUARY 2009
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16
ZERO FLAGS (PCM1753/55)
Zero-Detect Condition
Zero detection for either output channel is independent from the other channel. If the data for a given channel
remains at a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that
channel.
Zero Flag Outputs
If a zero-detect condition exists for one or more channels, the zero flag pins for those channels are set to a logic
1 state. There are zero flag pins for each channel, ZEROL (pin 12) and ZEROR (pin 11). These pins can be
used to operate external mute circuits, or used as status indicators for a microcontroller, audio signal processor,
or other digitally controlled function.
The active polarity of zero flag outputs can be inverted by setting the ZREV bit of control register 22 to 1. The
reset default is active-high output, or ZREV = 0.
The L-channel and R-channel common zero flag can be selected by setting the AZRO bit of control register
22 to 1. The reset default is independent zero flags for L-channel and R-channel, or AZRO = 0.
In the case of the PCM1755, ZEROL and ZEROR are open-drain outputs.
ZERO FLAG (PCM1754)
The PCM1754 has a ZERO flag pin, ZEROA (pin 11). ZEROA is the L-channel and R-channel common zero
flag pin. If the data for L-channel and R-channel remains at a 0 level for 1024 sampling periods (or LRCK clock
periods), ZEROA is set to a logic 1 state.
HARDWARE CONTROL (PCM1754)
The digital functions of the PCM1754 are capable of hardware control. Table 2 shows selectable formats,
Table 3 shows de-emphasis control, and Table 4 shows mute control.
Table 2. Data Format Select
FMT (PIN 15) DATA FORMAT
LOW 16- to 24-bit, I
2
S format
HIGH 16-bit right-justified
Table 3. De-Emphasis Control
DEMP (PIN 13) DE-EMPHASIS FUNCTION
LOW 44.1 kHz de-emphasis OFF
HIGH 44.1 kHz de-emphasis ON
Table 4. Mute Control
MUTE (PIN 14) MUTE
LOW Mute OFF
HIGH Mute ON
OVERSAMPLING RATE CONTROL (PCM1754)
The PCM1754 automatically controls the oversampling rate of the delta-sigma D/A converters with the system
clock rate. The oversampling rate is set to 64× oversampling with every system clock and sampling frequency.