Datasheet

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PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, f
S
= 44.1 kHz, system clock = 384 f
S
, and 24-bit data (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Logic Current
I
IH
High-level input current
(1)
V
IN
= V
DD
10 µ A
I
IL
Low-level input current
(1)
V
IN
= 0 V –10 µ A
I
IH
High-level input current
(2)
V
IN
= V
DD
65 100 µ A
I
IL
Low-level input current
(2)
V
IN
= 0 V –10 µ A
Output Logic Level
V
OH
High-level output voltage
(3)
I
OH
= –2 mA 2.4 Vdc
V
OL
Low-level output voltage
(3)
I
OL
= 2 mA 1 Vdc
DYNAMIC PERFORMANCE
(4) (5)
PCM1742E
V
OUT
= 0 dB, f
S
= 44.1 kHz 0.003% 0.008%
V
OUT
= 0 dB, f
S
= 96 kHz 0.004%
V
OUT
= 0 dB, f
S
= 192 kHz 0.005%
THD+N Total harmonic distortion + noise
V
OUT
= –60 dB, f
S
= 44.1 kHz 1.2%
V
OUT
= –60 dB, f
S
= 96 kHz 1.6%
V
OUT
= –60 dB, f
S
= 192 kHz 1.8%
EIAJ, A-weighted, f
S
= 44.1 kHz 94 100
Dynamic range A-weighted, f
S
= 96 kHz 98 dB
A-weighted, f
S
= 192 kHz 96
EIAJ, A-weighted, f
S
= 44.1 kHz 94 100
SNR Signal-to-noise ratio A-weighted, f
S
= 96 kHz 98 dB
A-weighted, f
S
= 192 kHz 96
f
S
= 44.1 kHz 91 98
Channel separation f
S
= 96 kHz 96 dB
f
S
= 192 kHz 94
Level linearity error V
OUT
= –90 dB ±0.5 dB
(1) Pins 1, 2, 3, 16 (SCK, BCK, LRCK, DATA).
(2) Pins 13–15 (MD, MC, ML).
(3) Pins 11, 12 (ZEROR, ZEROL).
(4) Analog performance specifications are tested with a Shibasoku #725 THD meter with 400-Hz HPF on, 30-kHz LPF on, and an average
mode with 20-kHz bandwidth limiting. The load connected to the analog output is 5 k Ω or larger, via capacitive coupling.
(5) Conditions in 192-kHz operation are: system clock = 128 f
S
and oversampling rate = 64 f
S
(under register control).
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