Datasheet

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CONTROL INTERFACE TIMING REQUIREMENTS
50% of V
DD
50% of V
DD
50% of V
DD
ML
MC
MD
t
ML S
t
MCH
t
MCY
t
MDS
t
MDH
t
MCL
t
MHH
t
MLH
LSB
MODE CONTROL REGISTERS
User-Programmable Mode Controls
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
See Figure 25 for a detailed timing diagram of the serial control interface. These timing parameters are critical for
proper control port operation.
SYMBOL PARAMETER MIN TYP MAX UNIT
t
MCY
MC pulse cycle time 100 ns
t
MCL
MC low-level time 50 ns
t
MCH
MC high-level time 50 ns
t
MHH
ML high-level time 3/(256 × f
S
)
(2)
ns
t
MLS
ML falling edge to MC rising edge 20 ns
t
MLH
ML hold time
(1)
20 ns
t
MDH
MD hold time 15 ns
t
MDS
MD setup time 20 ns
(1) MC rising edge for LSB to ML rising edge
(2) f
S
= sampling rate
Figure 25. Control Interface Timing
The PCM1742 includes a number of user-programmable functions that are accessed via control registers. The
registers are programmed using the serial control interface that is discussed in a preceding section of this data
sheet. Table 2 lists the available mode control functions, along with their reset default conditions and associated
register index.
Table 2. User-Programmable Mode Controls
FUNCTION RESET DEFAULT CONTROL INDEX IDX[6:0]
REGISTER
Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps 0 dB, no attenuation 16 and 17 AT1[7:0], AT2[7:0]
Soft mute control Mute disabled 18 MUT[2:0]
Oversampling rate control (64 f
S
or 128 f
S
) 64-f
S
oversampling 18 OVER
DAC operation control DAC1 and DAC2 enabled 19 DAC[2:1]
De-emphasis function control De-emphasis disabled 19 DM12
De-emphasis sample rate selection 44.1 kHz 19 DMF[1:0]
Audio data format control 24-bit, left-justified 20 FMT[2:0]
Digital filter rolloff control Sharp rolloff 20 FLT
Zero-flag function select L-/R-channels independent 22 AZRO
Output phase select Normal phase 22 DREV
Zero-flag polarity select High 22 ZREV
16