Datasheet

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LRCK
BCK
DATA
50% of V
DD
50% of V
DD
50% of V
DD
t
BCH
t
BCL
t
LB
t
BL
t
DS
t
DH
t
BCY
PCM1742
SBAS176A – DECEMBER 2000 – REVISED APRIL 2005
SYMBOL DESCRIPTION MIN MAX UNIT
t
BCY
BCK pulse cycle time 1/(64 f
S
)
(1)
t
BCH
BCK high-level time 35 ns
t
BCL
BCK low-level time 35 ns
t
BL
BCK rising edge to LRCK edge 10 ns
t
LB
LRCK falling edge to BCK rising edge 10 ns
t
DS
DATA setup time 10 ns
t
DH
DATA hold time 10 ns
(1) f
S
is the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.).
Figure 22. Audio Interface Timing
14