Datasheet

www.ti.com
t=1/(64 44.1kHz)´
DATAL
DATAR
BCK
D0 D1 D2 D3 D4
T0229-01
t
w(BCH)
t
w(BCL)
t
(BCY)
BCK
DATAL
DATAR
t
(DS)
1.4V
1.4V
T0010-11
t
(DH)
PCM1738
SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007
Figure 45. Normal Data Output Form From DSD Decoder
PARAMETER MIN MAX UNIT
t
(BCY)
BCK clock cycle time 85
(1)
ns
t
w(BCH)
BCK high-level time 30 ns
t
w(BCL)
BCK low-level time 30 ns
t
(DS)
DATAL, DATAR setup time 10 ns
t
(DH)
DATAL, DATAR hold time 10 ns
(1) 2.8224 MHz × 4. (2.8224 MHz = 64 × 44.1 kHz. This value is specified at the DSD sampling rate.)
Figure 46. Timing for DSD Audio Interface
37
Submit Documentation Feedback