Datasheet
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REGISTER DEFINITIONS
PCM1738
SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007
Table 4. Mode Control Register Map
REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
16 W/R 0 0 1 0 0 0 0 ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0
17 W/R 0 0 1 0 0 0 1 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
18 W/R 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE
19 W/R 0 0 1 0 0 1 1 REV ATS1 ATS0 OPE CLKD CLKE FLT INZD
20 W/R 0 0 1 0 1 0 0 RSV
(1)
SRST MRST DFTH MONO CHSL OS1 OS0
21 R 0 0 1 0 1 0 1 RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
RSV
(1)
ZFGR ZFGL
(1) RSV is assigned for factory test operation.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 16 W/R 0 0 1 0 0 0 0 ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0
REGISTER 17 W/R 0 0 1 0 0 0 1 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
W/R Read/Write Mode Select
When W/R = 0, a write operation is performed.
When W/R = 1, a read operation is performed.
Default value: 0
ATL/R[7:0] Digital Attenuation Level Setting
These bits are read/write.
Default value: 1111 1111b
Each DAC output has a digital attenuator associated with it. The attenuator may be set from 0
db to –120 dB, in 0.5-dB steps. Alternatively, the attenuator may be set to infinite attenuation (or
mute).
The attenuation data for each channel can be set individually. However, the data load control
(ATLD bit of mode control register 18) is common to both attenuators. ATLD must be set to 1 in
order to change an attenuator's setting. The attenuation level may be set using the following
formula:
Attenuation level (dB) = 0.5 dB × (ATL/R[7:0]
DEC
– 255)
where ATL/R[7:0]
DEC
= 0 through 255
For ATL/R[7:0]
DEC
= 0 through 14, the attenuator is set to infinite attenuation.
The following table shows attenuator levels for various settings.
ATL/R[7:0] Decimal Value Attenuator Level Setting
1111 1111b 255 0 dB, no attenuation (default)
1111 1110b 254 –0.5 dB
1111 1101b 253 –1 dB
• • •
• • •
0001 0000b 16 119.5 dB
0000 1111b 15 120 dB
0000 1110b 14 Mute
• • •
• • •
0000 0000b 0 Mute
23
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