Datasheet

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t
w(BCH)
t
w(BCL)
t
(LB)
t
(BCY)
LRCK
BCK
DATA
t
(DS)
1.4V
1.4V
1.4V
T0010-10
t
(DH)
t
(BL)
HighImpedance
WhenReadModeisInstructed
A0
D7
D6
D4
D5
D3
D2 D1
D0
D7
D6
D4
D5
D3
D2 D1
D0
W/R
A1A2
A3
A4
A5
A6
CS
MC
MDI
MDO
T0048-05
PCM1738
SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007
PARAMETER MIN MAX UNIT
t
(BCY)
BCK clock cycle time 70 ns
t
w(BCL)
BCK low-level time 30 ns
t
w(BCH)
BCK high-level time 30 ns
t
(BL)
BCK rising edge to LRCK edge 10 ns
LRCK falling edge to BCK rising
t
(LB)
10 ns
edge
t
(DS)
DATA setup time 10 ns
t
(DH)
DATA hold time 10 ns
– LRCK clock duty cycle 50% – 2 bit clocks 50% + 2 bit clocks
Figure 36. Audio Interface Timing
NOTE: B15 is used for the selection of write or read. Setting W/R = 0 indicates a write, while W/R = 1 indicates a read.
B14–B8 are used for the register address.
B7–B0 are used for frgister data.
Figure 37. Serial Control Format
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