Datasheet

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t
w(SCKH)
t
w(SCKL)
System Clock
2 V
0.8 V
H
L
T0005-13
t
(SCK)
Reset
T0014-11
ResetRemoval
1024SystemClocks
V
DD
2.4V(Max)
2V(Typ)
1.6V(Min)
InternalReset
SystemClock
Reset
T0015-07
ResetRemoval
1024SystemClocks
InternalReset
SystemClock
(Pin1)RST
t
w(RST)
50%ofV
DD
PCM1738
SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007
PARAMETER MIN MAX UNIT
t
(SCK)
System clock cycle time 13 ns
t
w(SCKH)
System clock pulse duration, HIGH 5 ns
t
w(SCKL)
System clock pulse duration, LOW 5 ns
Figure 32. System Clock Input Timing
Figure 33. Power-On-Reset Timing
PARAMETER MIN MAX UNIT
t
w(RST)
Reset pulse duration, LOW 20 ns
Figure 34. External Reset Timing
16
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