Datasheet

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SYSTEM CLOCK AND RESET FUNCTIONS
SYSTEM CLOCK INPUT
SYSTEM CLOCK OUTPUT
POWER-ON AND EXTERNAL RESET FUNCTIONS
PCM1738
SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007
The PCM1738 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCKI input (pin 7). The PCM1738 has a system-clock detection
circuit that automatically senses if the system clock is operating at 128 f
S
to 768 f
S
. Table 2 shows examples of
system-clock frequencies for common audio sampling rates.
Figure 32 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. The PLL1700 multiclock generator is an excellent choice for
providing the PCM1738 system clock.
A buffered version of the system clock input is available at the SCKO output (pin 10). SCKO can operate at
either full (f
SCKI
) or half (f
SCKI
/2) rate. The SCKO output frequency may be programmed using the CLKD bit of
mode control register 19. The SCKO output pin can also be enabled or disabled using the CLKE bit of mode
control register 19. The default is SCKO enabled.
The PCM1738 includes a power-on-reset function (see Figure 33 ). The system clock input at SCKI should be
active for at least one clock period prior to V
DD
= 2 V. With the system clock active, and V
DD
> 2 V, the
power-on-reset function is enabled. The initialization sequence requires 1024 system clocks from the time V
DD
>
2 V. After the initialization period, the PCM1738 is set to its reset default state, as described in the Mode Control
Registers section of this data sheet.
The PCM1738 also includes an external reset capability using the RST input (pin 1). This allows an external
controller or master reset circuit to force the PCM1738 to initialize to its reset default state.
See Figure 34 for external reset operation and timing. The RST pin is set to a logic 0 for a minimum of 20 ns.
The RST pin is then set to a logic-1 state that starts the initialization sequence that requires 1024 system clock
periods. After the initialization sequence is complete, the PCM1738 is set to its reset default state, as described
in the Mode Control Registers section of this data sheet.
The external reset is especially useful in applications where there is a delay between PCM1738 power up and
system-clock activation. In this case, the RST pin should be held at a logic-0 level until the system clock has
been activated. The RST pin may then be set to a logic-1 state to start the initialization sequence.
Table 2. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)
FREQUENCY
128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
32 kHz 4.096 6.144 8.192 12.288 16.384 24.576
44.1 kHz 5.6488 8.4672 11.2896 16.9344 22.5792 33.8688
48 kHz 6.144 9.216 12.288 18.432 24.576 36.864
96 kHz 12.288 18.432 24.576 36.864 49.152 73.728
192 kHz 24.576 36.864 49.152 73.728
(1) (1)
(1) This system clock is not supported for the given sampling frequency.
15
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