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ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SSOP 28

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PCM1738

FEATURES APPLICATIONS

DESCRIPTION

PCM1738

SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007

24-Bit, 192-kHz Sampling, Advanced Segment, Audio-Stereo Digital-to-Analog Converter

• AV Receivers

• 24-Bit Resolution

• DVD Movie Players

• Analog Performance (V

= 5 V):

• SACD Players

– Dynamic Range: 117 dB (typical)

• HDTV Receivers

– SNR: 117 dB (typical)

• Car Audio Systems

– THD+N: 0.0004% (typical)

• Digital Multitrack Recorders

– Full-Scale Output: 2.2 Vrms (at

• Other Multichannel Audio Systems

Postamplifier)

• Differential Current Output: ± 2.48 mA

• Sampling Frequency: 10 kHz to 200 kHz

The PCM1738 is a CMOS, monolithic, integrated

• System Clock: 128, 192, 256, 384, 512, or 768

circuit (IC) that includes stereo digital-to-analog

With Autodetect

converters (DACs) and support circuitry in a small

SSOP-28 package. The data converters use a newly

• Accepts 16-, 20-, and 24-Bit Audio Data

developed advanced segment DAC architecture to

• Data Formats: Standard, I

S, and Left-Justified

achieve excellent dynamic performance and

• 8 × Oversampling Digital Filter:

improved tolerance to clock jitter. The PCM1738

– Stop-Band Attenuation: –82 dB

provides balanced current outputs, allowing the user

to optimize analog performance externally, and

– Pass-Band Ripple: ± 0.002 dB

accepts industry-standard audio data formats with

• Optional Interface to External Digital Filter

16- to 24-bit data, providing easy interfacing to audio

Available

DSP and decoder chips. Sampling rates up to 200

• Optional Interface to DSD Decoder for SACD

kHz are supported. The PCM1738 also has two

optional modes of operation: an external digital filter

Playback

mode (for use with the DF1704, DF1706, and

• User-Programmable Mode Controls:

PMD200), and a DSD decoder interface for SACD

– Digital Attenuation: 0 dB to –120 dB, 0.5

playback applications. A full set of

dB/Step

user-programmable functions is accessible through a

4-wire serial control port that supports register write

– Digital De-Emphasis

and read functions.

– Digital Filter Rolloff: Sharp or Slow

– Soft Mute

– Zero-Detect Mute

– Zero Flags for Each Output

• Dual-Supply Operation:

– 5-V Analog, 3.3-V Digital

• 5-V Tolerant Digital Inputs

• Small SSOP-28 Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Audio Precision, System Two are trademarks of Audio Precision, Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (46 pages)

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PC M1 738 PCM1738 SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 24-Bit, 192-kHz Sampling, Advanced Segment, Audio-Stereo Digital-to-Analog Converter FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • 24-Bit Resolution Analog Performance (VCC = 5 V): – Dynamic Range: 117 dB (typical) – SNR: 117 dB (typical) – THD+N: 0.0004% (typical) – Full-Scale Output: 2.2 Vrms (at Postamplifier) Differential Current Output: ±2.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted) PARAMETER TEST CONDITIONS PCM1738E MIN TYP UNIT MAX DIGITAL INPUT/OUTPUT Logic family VIH TTL compatible 2 Input logic level VIL IIH Input logic current IIL VOH Output logic level VOL IOHZ High-impedance output logic current (1) IOLZ 0.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted) PARAMETER TEST CONDITIONS PCM1738E MIN TYP MAX UNIT DIGITAL-FILTER PERFORMANCE Filter Characteristics 1, Sharp Rolloff Pass band ±0.002 dB Pass band –3 dB Stop band 0.454 fS Hz 0.49 fS Hz 0.546 fS Hz ±0.
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PCM1738 www.ti.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 Table 1. TERMINAL FUNCTIONS TERMINAL TYPE DESCRIPTION 18 — Analog ground 1 27 — Analog ground 2 CS 14 IN Chip select and latch for mode control (1) BCK 6 IN Bit-clock input. Connected to GND for DSD mode (1) DATA 5 IN Serial audio data input for normal operation.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted). DIGITAL FILTER De-Emphasis Off, fS = 44.1kHz FREQUENCY RESPONSE (Sharp Rolloff) PASS-BAND RIPPLE (Sharp Rolloff) 0.003 0 −20 0.002 0.001 −60 Amplitude − dB Amplitude − dB −40 −80 −100 0 −0.001 −120 −0.002 −140 −0.003 0.0 −160 0 1 2 3 4 Frequency [× fS] 0.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted). De-Emphasis Filter DE-EMPHASIS DE-EMPHASIS ERROR 0 0.5 fS = 32 kHz 0.4 −2 0.3 De-Emphasis Error − dB De-Emphasis Level − dB fS = 32 kHz −1 −3 −4 −5 −6 −7 0.2 0.1 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 −0.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted). DE-EMPHASIS DE-EMPHASIS ERROR 0 0.5 fS = 48 kHz 0.4 −2 0.3 De-Emphasis Error − dB De-Emphasis Level − dB fS = 48 kHz −1 −3 −4 −5 −6 −7 0.2 0.1 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −0.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted). DYNAMIC RANGE vs VCC 120 119 119 fS = 96 kHz fS = 44.1 kHz 117 116 115 115 113 113 5.00 5.25 112 −40 5.50 VCC − Supply Voltage − V G013 20 40 60 80 SIGNAL-TO-NOISE RATIO vs VCC SIGNAL-TO-NOISE RATIO vs TEMPERATURE 120 119 119 fS = 44.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted). CHANNEL SEPARATION vs VCC CHANNEL SEPARATION vs TEMPERATURE 118 118 117 117 116 Channel Separation − dB Channel Separation − dB 116 fS = 44.1 kHz 115 114 113 fS = 96 kHz 112 111 fS = 44.1 kHz 115 114 fS = 96 kHz 113 112 111 110 4.50 4.75 5.00 5.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 256 fS (fS = 44.1 kHz), and 24-bit input data (unless otherwise noted). THD+N vs LEVEL (PCM MODE) THD+N − Total Harmonic Distortion + Noise − % 100 10 1 fS = 96 kHz 0.1 fS = 44.1 kHz 0.01 0.001 0.0001 −100 −80 −60 −40 −20 0 Input Level − dBFS G021 Figure 21. All specifications at TA = 25°C, VDD = 3.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 ANALOG FIR FILTER PERFORMANCE FOR DSD MODE All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 11.2896 MHz (44.1 kHz × 256 fS), and 50% modulation DSD data input (unless otherwise noted) DSD FILTER 1 DSD FILTER 1 0 0 −1 −20 Gain − dB Gain − dB −2 −3 −40 −60 −4 −80 −5 −100 −6 0 50 100 150 0 200 500 1000 1500 f − Frequency − kHz f − Frequency − kHz G025 G024 Figure 24. Figure 25.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 ANALOG FIR FILTER PERFORMANCE FOR DSD MODE (continued) All specifications at TA = 25°C, VDD = 3.3 V, VCC = 5 V, SCKI = 11.2896 MHz (44.1 kHz × 256 fS), and 50% modulation DSD data input (unless otherwise noted) DSD FITLER 3 DSD FITLER 3 0 0 −1 −20 Gain − dB Gain − dB −2 −3 −40 −60 −4 −80 −5 −100 −6 0 50 100 150 0 200 500 1000 1500 f − Frequency − kHz f − Frequency − kHz G029 G028 Figure 28. Figure 29.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 SYSTEM CLOCK AND RESET FUNCTIONS SYSTEM CLOCK INPUT The PCM1738 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCKI input (pin 7). The PCM1738 has a system-clock detection circuit that automatically senses if the system clock is operating at 128 fS to 768 fS. Table 2 shows examples of system-clock frequencies for common audio sampling rates.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 tw(SCKH) H 2V System Clock 0.8 V L tw(SCKL) t(SCK) T0005-13 PARAMETER MIN MAX UNIT t(SCK) System clock cycle time 13 ns tw(SCKH) System clock pulse duration, HIGH 5 ns tw(SCKL) System clock pulse duration, LOW 5 ns Figure 32. System Clock Input Timing VDD 2.4 V (Max) 2 V (Typ) 1.6 V (Min) Reset Reset Removal Internal Reset 1024 System Clocks System Clock T0014-11 Figure 33.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 AUDIO DATA INTERFACE AUDIO SERIAL INTERFACE The audio serial interface for the PCM1738 consists of a 3-wire synchronous serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, used to clock the serial data present on DATA into the audio interface serial shift register. Serial data is clocked into the PCM1738 on the rising edge of BCK.
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PCM1738 www.ti.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 1.4 V LRCK tw(BCL) tw(BCH) t(LB) 1.4 V BCK t(BL) t(BCY) 1.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 EXTERNAL DIGITAL FILTER INTERFACE AND TIMING The PCM1738 supports an external digital-filter interface comprised of a 4-wire synchronous serial port that allows the use of an external digital filter. External filters include the DF1704 and DF1706 from Texas Instruments, the Pacific Microsonics PMD200, or a programmable digital signal processor.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 tw(MHH) 1.4 V CS t(MSS) tw(MCL) t(MSH) tw(MCH) 1.4 V MC t(MCY) LSB 1.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 Table 3. User-Programmable Mode Controls FUNCTION DEFAULT REGISTER BIT 16 for L-channel 17 for R-channel ATL[7:0] ATR[7:0] FUNCTIONS AVAILABLE FOR BOTH WRITE AND READ Digital attenuation control 0 dB to –120 dB in 0.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 Table 4.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 REGISTER 18 W/R B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 W/R 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE Read/Write Mode Control When W/R = 0, a write operation is performed. When W/R = 1, a read operation is performed. Default value: 0 ATLD Attenuation Load Control This bit is read/write.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 DMF[1:0] Sampling Frequency Selection for the De-Emphasis Function These bits are read/write. Default value: 00 DMF[1:0] De-Emphasis Same Rate Selection 00 Disabled (default) 01 48 kHz 10 44.1 kHz 11 32 kHz The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is enabled by setting the DME bit.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 REGISTER 19 W/R B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 W/R 0 0 1 0 0 1 1 REV ATS1 ATS0 OPE CLKD CLKE FLT INZD Read/Write Mode Control When W/R = 0, a write operation is performed. When W/R = 1, a read operation is performed. Default value: 0 REV Output Phase Reversal This bit is read/write.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 CLKE SCKO Output Enable This bit is read/write. Default value: 0 CLKE = 0 SCKO enabled (default) CLKE = 1 SCKO disabled The CLKE bit is used to enable or disable the system clock output pin, SCKO. FLT Digital Filter Rolloff Control This bit is read/write. Default value: 0 FLT = 0 Sharp rolloff (default) FLT = 1 Slow rolloff The FLT bit allows the user to select the digital filter rolloff characteristics.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 REGISTER 20 W/R B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 W/R 0 0 1 0 1 0 0 RSV SRST MRST DFTH MONO CHSL OS1 OS0 Read/Write Mode Control When W/R = 0, a write operation is performed. When W/R = 1, a read operation is performed. Default value: 0 SRST System Reset Control This bit is read/write.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 CHSL Channel Selection for Monaural Mode This bit is read/write. Default value: 0 This bit is available when MONO = 1. CHSL = 0 L-channel selected (default) CHSL = 1 R-channel selected The CHSL bit is used to set the audio data selection for the monaural mode. OS[1:0] Delta-Sigma Oversampling Rate Selection These bits are available for read/write.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 TYPICAL CONNECTION DIAGRAM IN PCM MODE Controller 5V 15 V –15 V PCM1738E 28 ZEROL AGND2 27 3 ZEROR IOUTL– 26 L/R Clock (fS) 4 LRCK IOUTL+ 25 Audio DATA 5 DATA VCC2 24 Bit Clock 6 BCK VCC1 23 System Clock 7 SCKI VCOM3 22 8 DGND IREF 21 9 VDD VCOM2 20 10 SCKO VCOM1 19 11 MDO AGND1 18 12 MDI IOUTR+ 17 13 MC IOUTR– 16 14 CS MUTE 15 + RST 2 + VOUT L-Channel + + 3.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 ANALOG OUTPUTS +5V PCM1738E C13 0.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 Analog Gain by Balanced Amplifier The I/V converters are followed by balanced amplifier stages that sum the differential signals for each channel, creating a single-ended voltage output. In addition, the balanced amplifiers provide a second-order, low-pass filter function that band-limits the audio output signal. The cutoff frequency and gain is given by external R and C component values.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 The external digital-filter application mode is available by programming the following bits in the corresponding mode control registers: DFTH = 1 (register 20) DME = 0 (register 18) The pins used to provide the serial interface for the external digital filter are shown in the application diagram of Figure 41.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 1.4 V WDCK t(BCL) t(BCH) t(LB) 1.4 V BCK t(BL) t(BCY) DATAL DATAR 1.4 V t(DH) t(DS) T0199-01 PARAMETER MIN MAX UNIT t(BCY) BCK clock cycle time 18 ns tw(BCL) BCK pulse duration, LOW 7 ns tw(BCH) BCK pulse duration, HIGH 7 ns t(BL) BCK rising edge to WDCK falling edge 5 ns t(LB) WDCK falling edge to BCK rising edge 5 ns t(DS) DATA setup time 5 ns t(DH) DATA hold time 5 ns Figure 43.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 OS[1:0] Delta-Sigma Oversampling Rate Selection These bits are available for read/write. Default Value: 00 OS[1:0] Operation Speed Select 00 8 × fWDCK (default) 01 Reserved 10 16 × fWDCK 11 4 × fWDCK The effective oversampling rate is determined by the oversampling performed by both the external digital filter and the delta-sigma modulator.
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PCM1738 www.ti.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 t = 1/(64 ´ 44.1 kHz) BCK DATAL DATAR D0 D1 D2 D3 D4 T0229-01 Figure 45. Normal Data Output Form From DSD Decoder tw(BCL) tw(BCH) 1.4 V BCK t(BCY) DATAL DATAR 1.4 V t(DH) t(DS) T0010-11 PARAMETER MIN MAX UNIT t(BCY) BCK clock cycle time 85(1) ns tw(BCH) BCK high-level time 30 ns tw(BCL) BCK low-level time 30 ns t(DS) DATAL, DATAR setup time 10 ns t(DH) DATAL, DATAR hold time 10 ns (1) 2.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 DSD-MODE CONFIGURATION AND FUNCTION CONTROLS Configuration for DSD interface mode: • DFTH = 1 (register 20) • DME = 1 (register 18) Table 6 shows the register mapping available in DSD mode. Table 6.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 APPLICATION FOR MONAURAL-MODE OPERATION Single-channel signals within stereo-audio data input are output to both IOUTL and IOUTR as differential outputs. Selection of channels to output is available with the CHSL bit in register 20. Applications, such as monaural operation,are useful for high-end audio applications to provide over 120 dB for dynamic range. A typical MONO mode application is shown in Figure 47.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 THEORY OF OPERATION ADVANCED SEGMENT DAC Upper 6 Bits 0–62 Level ICOB Decoder 0–66 Digital Input + Advanced DWA 24-Bit 8fS MSB and Lower 18 Bits 3rd-Order, 5-Level, Delta-Sigma Current Segment DAC Analog Output 0–4 Level B0204-01 Figure 48. Architecture of Advanced Segment DAC The PCM1738 uses the newly developed advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 Analog Power Digital Power +VD AGND +5VA DGND +VS –VS REG VCC VDD Digital Logic and Audio Processor Output Circuits DGND Digital Ground PCM1738 AGND Digital Section Analog Ground Analog Section Return Path for Digital Signals B0031-07 Figure 49.
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PCM1738 www.ti.com SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007 BYPASS AND DECOUPLING CAPACITOR REQUIREMENTS Various sized decoupling capacitors can be used, with no special tolerances being required. All capacitors should be located as close as physically possible to the power supply and reference pins of the PCM1738 to reduce noise pickup from surrounding circuitry.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1738E/2K Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.5 10.8 2.4 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1738E/2K SSOP DB 28 2000 336.6 336.6 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.