Datasheet
®
9
PCM1725
FIGURE 10. 5-Level ∆Σ Modulator Block Diagram.
FIGURE 11. Quantization Noise Spectrum.
Out
48f
S
(384f
S
)
64f
S
(256f
S
)
In
8f
S
18-Bit
+
++
4
3
2
1
0
5-level Quantizer
+
–
+
Z
–1
+
–
+
Z
–1
+
+
Z
–1
THEORY OF OPERATION
The delta-sigma section of PCM1725 is based on a 5-level
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level delta-
sigma format. A block diagram of the 5-level delta-sigma
modulator is shown in Figure 10. This 5-level delta-sigma
modulator has the advantage of stability and clock jitter over
the typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8X interpolation filter is 96f
S
for a
384f
S
system clock, and 64f
S
for a 256f
S
system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 11.
5-LEVEL ∆Σ MODULATOR
Frequency (kHz)
Gain (–dB)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0 5 10 15 20 25
Not Recommended For New Designs