Datasheet

®
11 PCM1716
forced to a bipolar zero state (V
CC
/2). The zero detection
feature is used to avoid noise which may occur when the
input is DC. When the output is forced to bipolar zero,
there may be an audible click. PCM1716 allows the zero
detect feature to be disabled so the user can implement an
external muting circuit.
SRO (B3) is roll-off performance of digital filter selection.
SRO = L Sharp Roll-Off
SRO = H Slow Roll-Off
ATC (B2) is used as an attenuation control. When bit 3 is
set HIGH, the attenuation data on Register 0 is used for
both channels, and the data in Register 1 is ignored. When
bit 3 is LOW, each channel has separate attenuation data.
ATC = L Ch Individual ATT Control
ATC = H Common ATT Control
Bits 0 (I
2
S) and 1 (LRP) are used to control the input data
format. A “LOW” on bit 0 sets the format to (MSB-first,
right-justified Japanese format) and a “HIGH” sets the
format to I
2
S (Philips serial data protocol). Bit 1 (LRP) is
used to select the polarity of LRCIN (sample rate clock).
When bit 1 is “LOW”, left channel data is assumed when
LRCIN is in a “HIGH” phase and right channel data is
assumed when LRCIN is in a “LOW” phase. When bit 1 is
“HIGH”, the polarity assumption is reversed.
LRP = L L R H/Lch
LRP = H L R L/Lch
FIGURE 8. Program Register Input Timing.
IZD (B8)
B8 = L Zero Detect Mute OFF
B8 = H Zero Detect Mute ON
Bits 6 (SF0) and 7 (SF1) are used to select the sampling
frequency for De-emphasis.
SF1 SF0 Sampling Rate
0 0 Reserved
0 1 48kHz
1 0 44.1kHz
1 1 32kHz
CKO (B5) is output frequency control at CLKO pin, can be
selected as Buffer (1/1) or half rate of input frequency
(1/2).
CKO = L Buffer Out of XTi Clock
CKO = H Half (1/2) Frequency Out of XTi Clock
REF (B4) is output analog signal phase control.
REV = L Normal Output
REV = H Inverted Output
1.4V
1.4V
1.4V
ML
MC
MD
t
MLH
t
MCH
t
MCL
t
MDS
t
MCY
t
MLS
t
MLL
t
MHH
1.4V
CS
t
CSML
t
MLCS
t
MDH
LSB
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Hold Time
MD Set-up Time
ML Low Level Time
ML High Level Time
ML Hold Time
ML Set-up Time
CS Low to ML Low Time
(2)
ML High to CS High Time
(2)
NOTE: (1) System Clock Cycle. (2) CS Should be changed during ML = H.
: t
MCY
: t
MCL
: t
MCH
: t
MDH
: t
MDS
: t
MLL
: t
MHH
: t
MLH
: t
MLS
: t
CSML
: t
MLCS
: 100ns (min)
: 40ns (min)
: 40ns (min)
: 40ns (min)
: 40ns (min)
: 40ns (min) + 1SYSCLK
(1)
(min)
: 40ns (min) + 1SYSCLK
(1)
(min)
: 40ns (min)
: 40ns (min)
: 10ns (min)
: 10ns (min)
Not Recommended For New Designs