Datasheet

®
8
PCM1704
Input Data Inversion
INVERT (pin 10) is used to select the phase of the input data
presented to the DAC. Table III shows the two options. Pin
10 is internally pulled up to DGND, and therefore defaults
to normal, or non-inverting data.
APPLICATIONS INFORMATION
POWER SUPPLIES
For this discussion, please refer to the internal connection
diagram for the PCM1704 in Figure 3. The PCM1704 only
requires a ±5V supply for operation. Both positive supplies
(+V
DD
and +V
CC
) should be tied together at a single point
and connected to a single +5V analog power supply. Simi-
larly, both negative supplies (–V
DD
and –V
CC
) should be tied
at a single point and connected to a single –5V analog power
INVERT (Pin 10) PHASE
INVERT = H (DGND) Normal (non-inverted)
INVERT = L (–V
DD
) Inverted
TABLE III. Input Data Phase Selection.
supply. No advantage is gained by using separate analog and
digital power supplies. It is more important that the analog
supplies used to drive these pins are as noise and ripple free
as possible to reduce coupling of supply noise to the output.
Power supply decoupling capacitors should be used at each
supply pin to maximize power supply rejection, as shown in
Figure 3. All ground pins (AGND and DGND) should be
connected to an analog ground plane as close to the PCM1704
as possible. The PCM1704 should reside entirely over the
analog ground plane of the printed circuit board.
Bypass and Decoupling Capacitor Requirements
Various-sized decoupling capacitors can be used, with no
special tolerances being required. Figure 5 shows typical
values used by Burr-Brown on our evaluation fixture, which
designers can use as recommended values. All capacitors
should be located as close to the appropriate pins of the
PCM1704 as possible to reduce noise pickup from sur-
rounding circuitry. Aluminum electrolytic capacitors are
recommended for larger values, while metal-film or mono-
lithic ceramic capacitors are used for smaller values.
FIGURE 3. PCM1704 Internal Connection Diagram.
Interface
Logic
and
Logic Bias
23-Bit
Segment
Switches
Reference,
Servo
and
Bipolar
Offset
Analog
Bias
Logic
Bias
23-Bit
Current
Segments
BPO
DGND
–V
CC
AGND
I
OUT
BCLK
WCLK
DATA
–V
DD
+V
DD
+V
CC
+5V Supply
BPO DC
SERVO DC
REF DC
+
+
+
+
+
+
+
–5V Supply
2mA 3mA
20mA 10mA