Datasheet

®
7 PCM1704
AUDIO DATA INTERFACE
BASIC OPERATION
The audio interface of the PCM1704 accepts TTL-compat-
ible input levels. The data format at the DATA input of the
PCM1704 is Binary Two’s Complement, with the most
significant bit (MSB) being first in the serial input bit steam.
Table I shows the relationship between the audio input data
and DAC output for the PCM1704. Any number of bits can
precede the 24 bits to be loaded since only the last 24 bits
will be transferred to the parallel DAC register after WCLK
(pin 7) has gone LOW (logic 0).
Maximum Bit Clock (BCLK) Rate
The maximum BCLK rate is specified as 25MHz. This is
derived from the 8X oversampling of the PCM1704. Given
a 96kHz sampling rate, an 8X oversampling input and a
32-bit frame length, we get:
96kHz • 8 • 32 = 24.576MHz
“Stopped Clock” Operation
The PCM1704 is normally operated with a continuous
BCLK input. If BCLK is stopped between input data words,
the last 24 bits shifted in are not actually transferred from the
serial register to the parallel DAC register until WCLK goes
LOW. WCLK must remain LOW until after the first BCLK
cycle of the next data word to insure proper DAC operation.
The specified setup and hold times for DATA and WCLK
must be observed.
DATA FORMAT CONTROL
Data format is controlled by two pins on the PCM1704—the
20BIT and INVERT inputs. Their functions are described in
the following paragraphs and tables.
Input Word Length
20BIT (pin 9) is used to select the input data length. Table
II shows the available selections. Pin 9 is internally pulled
up to DGND and therefore, defaults to 24-bit data.
BINARY TWO’S COMPLEMENT
INPUT DATA (Hex) DAC OUTPUT
7FFFFF + Full Scale
000000 Bipolar Zero
FFFFFF Bipoar Zero – 1 LSB
800000 – Full Scale
TABLE I. Digital Input/DAC Output Relationships.
Audio data is supplied to the DATA (pin 1) input. The bit
clock is used to shift data into the PCM1704 and is supplied
to BCLK (pin 2). All DAC serial input data bits are latched
into the serial input register on the rising edge of BCLK. The
serial-to-parallel data transfer to the DAC occurs on the
falling edge of WCLK. The change in the output of the DAC
occurs at the rising edge of the 2nd BCLK after the falling
edge of WCLK. Figure 1 shows the audio data input format.
Figure 2 shows the input timing relationships.
FIGURE 1. Audio Input Data Format.
t
DS
t
BCH
t
BCY
t
DH
t
BCL
t
WCH
t
WCL
t
WH
t
WS
1.4V
1.4V
1.4V
WCLK
BCLK
DATA
FIGURE 2. Audio Input Data Timing.
BCLK Pulse Cycle Time t
BCY
40ns (min)
BCLK Pulse Width HIGH t
BCH
14ns (min)
BCLK Pulse Width LOW t
BCL
14ns (min)
BCLK Rising Edge to WCLK Falling Edge t
WH
10ns (min)
WCLK Falling Edge to BCLK Rising Edge t
WS
10ns (min)
WCLK Pulse Width HIGH t
WCH
> t
BCY
WCLK Pulse WIdth LOW t
WCL
> t
BCY
DATA Set-up Time t
DS
10ns (min)
DATA Hold Time t
DH
10ns (min)
20BIT (Pin 9) DATA WORD LENGTH
20BIT = H (DGND) 24-Bit Data Word
20BIT = L (–V
DD
) 20-Bit Data Word
TABLE II. Input Word Length Selection.
B1 B2 B3
B22 B23
MSB LSB
B24
WCLK
DATA
DAC Output
BCK
DATA (20-Bit)
DATA (24-Bit)
LSB
B1 B2 B3
B18 B19
MSB
B20