Datasheet

AUDIO INTERFACE TIMING
BCK
(Input)
1.4V
1.4V
1.4V
t
LRS
LRCK
(Input)
DIN1/2/3/4
t
DIH
t
LRH
t
DIS
t
BCH
t
BCL
t
BCY
t
LRS
1.4V
1.4V
1.4V
BCK
(Input)
LRCK
(Input)
DIN1/2/3/4
t
BCH
t
BCL
t
BCY
t
LRH
t
DIS
t
DIH
t
LRW
PCM1690
SBAS448A – OCTOBER 2008 – REVISED JANUARY 2009 .............................................................................................................................................. www.ti.com
Figure 29 and Figure 30 describe the detailed interface timing specifications.
Figure 29. Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I
2
S Data Formats
Table 6. Timing Requirements for Figure 29
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
BCY
BCK cycle time 75 ns
t
BCH
BCK pulse width high 35 ns
t
BCL
BCK pulse width low 35 ns
t
LRS
LRCK setup time to BCK rising edge 10 ns
t
LRH
LRCK hold time to BCK rising edge 10 ns
t
DIS
DIN1/2/3/4 setup time to BCK rising edge 10 ns
t
DIH
DIN1/2/3/4 hold time to BCK rising edge 10 ns
Figure 30. Audio Interface Timing Requirements for DSP and TDM Data Formats
Table 7. Timing Requirements for Figure 30
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
BCY
BCK cycle time 40 ns
t
BCH
BCK pulse width high 15 ns
t
BCL
BCK pulse width low 15 ns
LRCK pulse width high (DSP format) t
BCY
t
BCY
t
LRW
LRCK pulse width high (TDM format) t
BCY
1/f
S
– t
BCY
t
LRS
LRCK setup time to BCK rising edge 10 ns
t
LRH
LRCK hold time to BCK rising edge 10 ns
t
DIS
DIN1/2/3/4 setup time to BCK rising edge 10 ns
t
DIH
DIN1/2/3/4 hold time to BCK rising edge 10 ns
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