Datasheet

SYSTEM CLOCK INPUT
SystemClock
(SCKI)
High
Low
t
SCL
t
SCH
t
SCY
2.0V
0.8V
PCM1690
SBAS448A – OCTOBER 2008 – REVISED JANUARY 2009 .............................................................................................................................................. www.ti.com
The PCM1690 requires an external system clock input applied at the SCKI input for DAC operation. The system
clock operates at an integer multiple of the sampling frequency, or f
S
. The multiples supported in DAC operation
include 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
, 512 f
S
, 768 f
S
, and 1152 f
S
. Details for these system clock multiples are
shown in Table 2 . Figure 18 and Table 3 show the SCKI timing requirements.
Table 2. System Clock Frequencies for Common Audio Sampling Rates
SAMPLING
DEFAULT
FREQUENCY SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING
MODE f
S
(kHz) 128 f
S
192 f
S
256 f
S
384 f
S
512 f
S
768 f
S
1152 f
S
8 N/A N/A 2.0480 3.0720 4.0960 6.1440 9.2160
16 2.0480 3.0720 4.0960 6.1440 8.1920 12.2880 18.4320
Single rate 32 4.0960 6.1440 8.1920 12.2880 16.3840 24.5760 36.8640
44.1 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 N/A
48 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 N/A
88.2 11.2896 16.9344 22.5792 33.8688 N/A N/A N/A
Dual rate
96 12.2880 18.4320 24.5760 36.8640 N/A N/A N/A
176.4 22.5792 33.8688 N/A N/A N/A N/A N/A
Quad rate
192 24.5760 36.8640 N/A N/A N/A N/A N/A
Figure 18. System Clock Timing Requirements
Table 3. Timing Requirements for Figure 18
SYMBOL PARAMETER MIN MAX UNIT
t
SCY
System clock cycle time 27 ns
t
SCH
System clock width high 10 ns
t
SCL
System clock width low 10 ns
— System clock duty cycle 40 60 %
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Product Folder Link(s): PCM1690