Datasheet

APPLICATION INFORMATION
CONNECTION DIAGRAMS
SCK
24
23
22
21
20
19
18
17
16
15
5
6
7
8
9
10
11
12
13
14
PCM1680
DATA1
BCK
LRCK
V
DD
DGND
DATA2
DATA3
DATA4
MSEL
AGND2
AGND1
V
CC
2
V
OUT
3
V
OUT
4
V
OUT
5
V
CC
1
V
OUT
7
V
OUT
6
ZERO1
1
2
3
4
MS/ADR
MC/SCL
MD/SDA
28
27
26
25
ZERO2
V
OUT
1
V
OUT
2
V
COM
V
OUT
8
µC or µP
Audio DSP
or
Decoder
R
7
PLL170x
R
6
R
5
27-MHz
Master
Clock
R
4
R
2
R
3
R
1
C
9
5 V Analog
0 V
C
13
C
1
−C
8
: 4.7-µF to 10-µF Electrolytic Typical
C
9
−C
11
: 1-µF Ceramic Typical
C
12
, C
13
: 10-µF Electrolytic Typical
R
1
−R
7
: 22 Ω to 100 Ω Typical
+
C
1
+
C
2
+
C
12
C
11
C
10
+
C
3
+
C
4
+
C
5
+
C
6
+
C
7
+
C
8
L
R
LF
RF
RS
LS
CTR
SUB
Output
Low-Pass
Filter
S0057-01
+
PCM1680
www.ti.com .................................................................................................................................................. SLES133B – MARCH 2005 – REVISED OCTOBER 2008
A basic connection diagram is shown in Figure 32 , with the necessary power-supply bypassing and decoupling
components. Texas Instruments ’ PLL170x is used to generate the system clock input at SCK, as well as
generating the clock for the audio signal processor. The use of series resistors (22 Ω to 100 Ω ) is recommended
for SCK, LRCK, BCK, DATA1, DATA2, DATA3, and DATA4. The series resistor combines with the stray printed
circuit board (PCB) capacitance and device input capacitance to form a low-pass filter that removes
high-frequency noise from the digital signal, thus reducing high-frequency emission.
Figure 32. Basic Connection Diagram
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Product Folder Link(s): PCM1680