Datasheet

MODE CONTROL
SPI CONTROL INTERFACE
REGISTER WRITE OPERATION
MSB
0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D000
LSB
Register Index (or Address) Register Data
R0001-01
IDX0
D7 D6 D4D5 D3 D2 D1 D00
MS
MC
MD X 0
IDX6
X
IDX1IDX2IDX3IDX4IDX5IDX6
X
T0048-01
PCM1680
www.ti.com .................................................................................................................................................. SLES133B – MARCH 2005 – REVISED OCTOBER 2008
The PCM1680 has many programmable functions which can be controlled in the software control mode. The
functions are controlled by programming and reading the internal registers using the SPI or I
2
C interface. These
two interfaces for mode control can be selected by MSEL (pin 14). The functions of pins 2, 3, and 4 are changed
by MSEL selection as shown in Table 4 .
Table 4. Interface Mode Control
PIN FUNCTION
MSEL INTERFACE MODE
PIN 2 PIN 3 PIN 4
LOW SPI MS MC MD
HIGH I
2
C ADR SCL SCA
The SPI control interface of the PCM1680 is a 3-wire synchronous serial port that operates asynchronously to
the serial audio interface. The SPI control interface is used to program the on-chip mode registers. The control
interface includes MD (pin 4), MC (pin 3), and MS (pin 2). MD is the serial data input, used to program the mode
registers. MC is the control port for the serial bit clock, used to shift in the serial data, and MS is the control port
for mode control select, which is used to enable the mode control.
All write operations for the serial control port use 16-bit data words. Figure 24 shows the control data word
format. The most significant bit is a fixed ' 0 ' for the write operation. Seven bits, labeled IDX[6:0], set the register
index (or address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to
the register specified by IDX[6:0].
Figure 25 shows the functional timing diagram for writing to the serial control port. MS is held at a logic-1 state
until a register must be written. To start the register write cycle, MS is set to logic-0. 16 clock cycles are then
provided on MC, corresponding to the 16 bits of the control data word on MD. After the completion of the 16th
clock cycle, MS is set to logic-1 to latch the data into the indexed mode control register.
Figure 24. Control Data Word Format for MD
Figure 25. Write Operation Timing
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